Now using pll library to set the pll instead of "hard" setting

diff --git a/app/rama_dam/Makefile.omk b/app/rama_dam/Makefile.omk
index 983b8613708cdd2fb403dbee1fa3ea41e8ebea58..6a18f11e20cf7bc6439b974426a471818b3c1990 100644 (file)
--- a/app/rama_dam/Makefile.omk
+++ b/app/rama_dam/Makefile.omk
@@ -5,7 +5,7 @@ ifeq ($(BOARD),spejblarm)
 
 bin_PROGRAMS = rama_dam
 rama_dam_SOURCES = rama_dam.c
-rama_dam_LIBS = can uart_zen pwm
+rama_dam_LIBS = pll can uart_zen pwm
 link_VARIANTS = mpflash
 
 endif

diff --git a/app/rama_dam/rama_dam.c b/app/rama_dam/rama_dam.c
index de291a2a0dee5de56aeb1502e42173ea54c447b9..02fb5d0023559974aa5e08274e41bb481201c38f 100644 (file)
--- a/app/rama_dam/rama_dam.c
+++ b/app/rama_dam/rama_dam.c
@@ -14,6 +14,7 @@
 #include <types.h>
 #include <lpc21xx.h>
 #include <string.h>
+#include <pll.h>
 #include <periph/can.h>
 #include <periph/uart_zen.h>
 #include <pwm.h>
@@ -31,10 +32,15 @@
 #define SUB_VERSION 6
 /*! @} */
 
-/*!\def PCLK
-* Peripheral clock frequency in Hz.
+/*! @defgroup CLK Clock settings
+* @ingroup defines
+* These constants define the crystal frequency, core clock and peripheral clock.
+* @{
 */
+#define OSC_FREQ 10000000
+#define CCLK 60000000
 #define PCLK 60000000
+/*! @} */
 
 /*!\def TRUE
 * Formal definition of logical "TRUE" value.
@@ -990,10 +996,7 @@ int main ( void ) {
        
        can_msg_t reset_msg = {.id = DAM_RESET_ID, .dlc = 2, .data = {MAIN_VERSION, SUB_VERSION}}; // GPS CAN data packet
        
-       PLLCFG = 0x25;
-       PLLCON = 0x03; // set the core clock to 60MHz
-       PLLFEED = 0xAA;
-       PLLFEED = 0x55;
+       sys_pll_init ( CCLK, OSC_FREQ ); // set the core clock to 60MHz
        
        VPBDIV = 0x01; // peripheral clock = CPU clock (60MHz)