1 /* procesor H8S/2638 ver 1.1 */
5 #include <system_def.h>
9 #ifdef XRAM_SUPPORT_ENABLED
10 #define FULL_XRAM_ADRBUS
11 #endif /*XRAM_SUPPORT_ENABLED*/
12 #define SMALL_ADRBUS 8
14 static void deb_led_out(char val)
38 #if 1 /* registers setup */
39 /* Internal RAM enabled, advanced interrupt mode */
40 /* *SYS_SYSCR = 1*SYSCR_RAMEm | 1*SYSCR_INTM1m ; */
42 /* Remap 4kB of RAM from 0xffd000-0xffdfff to 0x0-0xfff */
43 /* *FLM_RAMER= 1*RAMER_RAMSm | 0&RAMER_RAMxm */
44 /* Sideefect - sets Flash software protection */
46 /* Enables access to flash control registers */
47 *IIC_SCRX |= SCRX_FLSHEm;
49 /* set shadow registers */
57 /* show something on debug leds */
61 *DIO_P3DR=0x09; /* Inactive value of TxD0 and TxD1 has to be log 1 */
62 SHADOW_REG_SET(DIO_P3DDR,0x01); /* TxD0 to output */
64 /* Setup system clock oscilator */
66 /* *SYS_LPWRCR=2&LPWRCR_STCxm; */
68 /* *SYS_LPWRCR=1&LPWRCR_STCxm; */
70 const char clkrat2stc[]={0,0/*1*/,1/*2*/,1,2/*4*/,2,2,2,3/*8*/};
71 *SYS_LPWRCR=LPWRCR_STCxm&(LPWRCR_STC0m*
72 clkrat2stc[(CPU_SYS_HZ+CPU_REF_HZ/2)/CPU_REF_HZ]);
77 /* No clock disable, immediate change, busmaster high-speed */
78 *SYS_SCKCR=(0*SCKCR_PSTOPm)|(1*SCKCR_STCSm)|(0&SCKCR_SCKxm);
81 /* Setup chipselect outputs CS4 CS5 CS6 */
83 SHADOW_REG_SET(DIO_P7DDR,1|2|4);
85 SHADOW_REG_SET(DIO_P7DDR,0);
88 /* Setup chipselect outputs CS3 CS2 CS1 CS0 */
89 // *DIO_PGDR |=2|4|8|0x10; no on 2638
91 SHADOW_REG_SET(DIO_PGDDR,2|4|8|0x10);
93 SHADOW_REG_SET(DIO_PGDDR,2|4);
97 /* setup chipselect 0 - FLASH */
98 *BUS_ABWCR&=~ABWCR_ABW0m; /* 16 bit width */
99 *BUS_ASTCR&=~ASTCR_AST0m; /* 2 states access */
100 *BUS_WCRL&=~(WCRL_W01m|WCRL_W00m);/* 0 additional wait states */
102 /* setup chipselect 1 - XRAM */
103 *BUS_ABWCR&=~ABWCR_ABW1m; /* 16 bit width */
104 *BUS_ASTCR&=~ASTCR_AST1m; /* 2 states access */
105 *BUS_WCRL&=~(WCRL_W11m|WCRL_W10m);/* 0 additional wait states */
108 /* setup chipselect 2 - SGM_LCD */
109 *BUS_ABWCR|=ABWCR_ABW2m; /* 8 bit width */
110 *BUS_ASTCR|=ASTCR_AST2m; /* 3 states access */
111 *BUS_WCRL&=~(WCRL_W21m|WCRL_W20m);/* 0 additional wait states */
112 *BUS_WCRL|=0*WCRL_W21m; /* 0/1 additional wait state */
114 /* setup chipselect 3 - SRAM */
115 *BUS_ABWCR|=ABWCR_ABW3m; /* 8 bit width */
116 *BUS_ASTCR|=ASTCR_AST3m; /* 3 states access */
117 *BUS_WCRL&=~(WCRL_W31m|WCRL_W30m);/* 0 additional wait states */
120 /* setup chipselect 4 - IDE */
121 *BUS_ABWCR&=~ABWCR_ABW4m; /* 16 bit width */
122 *BUS_ASTCR|=ASTCR_AST4m; /* 3 states access */
123 *BUS_WCRH&=~(WCRH_W41m|WCRH_W40m);/* 0 additional wait states */
125 /* setup chipselect 5 - IDE */
126 *BUS_ABWCR&=~ABWCR_ABW5m; /* 16 bit width */
127 *BUS_ASTCR|=ASTCR_AST5m; /* 3 states access */
128 *BUS_WCRH&=~(WCRH_W51m|WCRH_W50m);/* 0 additional wait states */
130 /* setup chipselect 6 - KL41 */
131 *BUS_ABWCR|=ABWCR_ABW6m; /* 8 bit width */
132 *BUS_ASTCR|=ASTCR_AST6m; /* 3 states access */
133 *BUS_WCRH=WCRH_W61m|WCRH_W60m; /* 3 additional wait states */
139 /* cross cs wait| rd/wr wait | no burst and DRAM */
140 *BUS_BCRH=0*BCRH_ICIS1m | 0*BCRH_ICIS0m;
141 /* release | no DMAC buffer | no external wait */
142 *BUS_BCRL=0*BCRL_BRLEm | 0*BCRL_WDBEm | 0*BCRL_WAITEm;
143 *DIO_PCDDR=0xff; /* A0-A7 are outputs */
145 *DIO_PBDDR=0xff; /* A8-A15 are outputs */
146 #endif /*SMALL_ADRBUS*/
147 #ifndef FULL_XRAM_ADRBUS
149 *SYS_PFCR=__val2mfld(PFCR_AExm,16-8); /* only 16 address lines */
150 #else /*SMALL_ADRBUS*/
151 *SYS_PFCR=__val2mfld(PFCR_AExm,SMALL_ADRBUS-8); /* only SMALL_ADRBUS address lines */
152 #endif /*SMALL_ADRBUS*/
153 #endif /* FULL_XRAM_ADRBUS */
155 #endif /* registers setup */
159 #ifdef FULL_XRAM_ADRBUS
160 /* Setup full 22 address lines */
162 *DIO_PADDR=0x0f; /* A16-A19 are outputs */
163 /* number of address output signals */
164 *SYS_PFCR=__val2mfld(PFCR_AExm,22-8);
165 #endif /*FULL_XRAM_ADRBUS*/