1 /*******************************************************************
2 Components for embedded applications builded for
3 laboratory and medical instruments firmware
5 system_def_h8canusb.h - definition of hardware adresses and registers
7 Copyright (C) 2002 by Pavel Pisa pisa@cmp.felk.cvut.cz
8 (C) 2002 by PiKRON Ltd. http://www.pikron.com
10 *******************************************************************/
12 #ifndef _SYSTEM_DEF_HW01_H_
13 #define _SYSTEM_DEF_HW01_H_
15 //#define CPU_REF_HZ 11059200l /* reference clock frequency */
16 //#define CPU_SYS_HZ 11059200l /* default system clock frequency */
18 //#define CPU_REF_HZ 18423000l /* reference clock for EDK2638 */
19 //#define CPU_SYS_HZ 18423000l /* default system for EDK2638 */
21 #define CPU_REF_HZ 5000000l /* reference clock for H8CANUSB */
22 #define CPU_SYS_HZ 20000000l /* default system for H8CANUSB */
25 unsigned long cpu_ref_hz; /* actual external XTAL reference */
26 unsigned long cpu_sys_hz; /* actual system clock frequency */
28 volatile unsigned long msec_time;
30 /* Keyboard KL41 (CS3) */
31 #define KL41_LCD_INST (volatile __u8 * const)(0x700000)
32 #define KL41_LCD_STAT (volatile __u8 * const)(0x700001)
33 #define KL41_LCD_WDATA (volatile __u8 * const)(0x700002)
34 #define KL41_LCD_RDATA (volatile __u8 * const)(0x700003)
35 #define KL41_LED_WR (volatile __u8 * const)(0x700001)
36 #define KL41_KBD_WR (volatile __u8 * const)(0x700003)
37 #define KL41_KBD_RD (volatile __u8 * const)(0x700004)
39 #define KL41_SUPPORT_ENABLED
43 /* SGM Small graphics LCD module 240x64 (CS3) */
44 #define SGM_LCD_DATA (volatile __u8 * const)(0x700000)
45 #define SGM_LCD_CMD (volatile __u8 * const)(0x700001)
46 #define SGM_LCD_STAT (volatile __u8 * const)(0x700001)
47 /* Keyboard on MO_KBD1 */
48 #define SGM_KBDI (volatile __u8 * const)(0x700002)
49 #define SGM_KBDO (volatile __u8 * const)(0x700002)
51 //#define SGM_SUPPORT_ENABLED
54 #define XRAM_START (volatile __u8 * const)(0x200000)
56 #define XRAM_SUPPORT_ENABLED
58 /* SRAM 32 kB (CS3) */
59 //#define SRAM_START (volatile __u8 * const)(0x610000)
63 #define ISR_USB_INTV EXCPTVEC_IRQ2 /* pin IRQ2 on PF.0 */
64 #define PDIUSB_TEST_IRQ() (!(*DIO_PORTF & 1))
65 #define PDIUSB_READ_DATA_ADDR (volatile __u8 * const)(0x500000)
66 #define PDIUSB_WRITE_DATA_ADDR (volatile __u8 * const)(0x500000)
67 #define PDIUSB_COMMAND_ADDR (volatile __u8 * const)(0x500001)
69 /* P1.0 .. DACK_N/DMACK0, P7.0 .. DMREQ/DREQ0, P7.2 .. EOT_N/TEND0 */
70 #undef PDIUSB_WITH_ADD_IRQ_HANDLER
71 #define PDIUSB_WITH_EXCPTVECT_SET
72 #define PDIUSB_SUPPORT_ENABLED
77 /* IDE (CS4) (CS5) powered by PF2 */
78 #define SIDE_START1 (volatile __u8 * const)(0x800000)
79 #define SIDE_START2 (volatile __u8 * const)(0xA00000)
80 #define IDE0_DATA (volatile __u16 * const)(SIDE_START1+0) /* DATA */
81 #define IDE0_ERROR (SIDE_START1+2) /* Error/Features RO/WO */
82 #define IDE0_NSECTOR (SIDE_START1+4) /* Sector Count R/W */
83 #define IDE0_SECTOR (SIDE_START1+6) /* SN, LBA 0-7 */
84 #define IDE0_LCYL (SIDE_START1+8) /* CL, LBA 8-15 */
85 #define IDE0_HCYL (SIDE_START1+10) /* CH, LBA 16-23 */
86 #define IDE0_CURRENT (SIDE_START1+12) /* 1L1DHHHH , LBA 24-27 */
87 #define IDE0_STATUS (SIDE_START1+14) /* Status */
88 #define IDE0_SELECT IDE0_CURRENT
89 #define IDE0_FEATURE IDE0_ERROR
90 #define IDE0_COMMAND IDE0_STATUS /* Command */
92 #define IDE0_DEVCTRL (SIDE_START2+12) /* used for resets */
93 #define IDE0_ALTSTATUS (SIDE_START2+14) /* IDE0_STATUS - no clear irq */
95 #define IDE0_SETPWR(pwr) do{ \
96 if(pwr) atomic_clear_mask_b1(4,DIO_PFDR); \
97 else atomic_set_mask_b1(4,DIO_PFDR); \
100 #define IDE0_PRESENT_M() ((*DIO_PORT9)&0x20)
102 #if (HW_VER_MAJOR == 0) && (HW_VER_MINOR == 2)
103 #define IDE_SWAP_BYTES
106 #define IDE0_SUPPORT_ENABLED
110 /* IRAM 16 kB of on-chip memory */
111 /* 0xffb000-0xffcfff .. 8 kB free */
112 /* 0xffd000-0xffdfff .. 4 kB for Flash emulation */
113 /* 0xffe000-0xffffc0 .. 4 kB - 64 B free*/
114 /* 0xffffc0-0xffffff .. 64 B free*/
115 #define IRAM_START (volatile __u8 * const)(0xffb000)
116 #define IRAM_START1 (volatile __u8 * const)(0xffe000)
117 #define FRAM_START (volatile __u8 * const)(0xffffc0)
120 /* SCI1 - IIC0 (P34, P35) */
123 /* SCI4 - RS232/485 */
126 /* IRQ1 - Index mark */
129 /* Some registers are read only on H8S processors */
130 /* We use shadow registers for some of them */
131 #define SHADOW_REG_ALT(_reg,_mask,_xor) \
132 (*(_reg)=_reg##_shadow=(_reg##_shadow&~(_mask))^(_xor))
134 #define SHADOW_REG_SET(_reg,_mask) \
135 (*(_reg)=_reg##_shadow|=(_mask))
137 #define SHADOW_REG_CLR(_reg,_mask) \
138 (*(_reg)=_reg##_shadow&=~(_mask))
140 #define SHADOW_REG_RD(_reg) \
143 #define SHADOW_REG_WR(_reg,_val) \
144 (*(_reg)=_reg##_shadow=(_val))
146 __u8 DIO_P1DDR_shadow;
147 __u8 DIO_P3DDR_shadow;
148 __u8 DIO_PFDDR_shadow;
149 __u8 DIO_PJDDR_shadow;
151 #define DEB_LED_INIT() \
154 SHADOW_REG_SET(DIO_PJDDR,0xee); /* set PJ.1, PJ.2, PJ.3 LED output */ \
157 #define DEB_LED_OFF(num) \
158 (*DIO_PJDR |= PJDR_PJ1DRm << (num))
159 #define DEB_LED_ON(num) \
160 (*DIO_PJDR &=~(PJDR_PJ1DRm << (num)))
163 #endif /* _SYSTEM_DEF_HW01_H_ */