1 /*******************************************************************
2 Components for embedded applications builded for
5 h8s2639h.h - internal peripherals registers of H8S2630,H8S2636,
7 internal comment: ver 1.2 (added HCAN masks)
8 *******************************************************************/
17 #define __PORT8 (volatile __u8 * const)
18 #define __PORT16 (volatile __u16 * const)
19 #define __PORT32 (volatile __u32 * const)
21 #else /* __ASSEMBLY__ */
25 #endif /* __ASSEMBLY__ */
28 //#define DTC_MRA __PORT8 0x????? /* DTC Mode Register A */
29 //#define MRA_SZm 0x01
30 //#define MRA_DTSm 0x02
31 //#define MRA_MD0m 0x04
32 //#define MRA_MD1m 0x08
33 //#define MRA_DM0m 0x10
34 //#define MRA_DM1m 0x20
35 //#define MRA_SM0m 0x40
36 //#define MRA_SM1m 0x80
37 //#define DTC_MRB __PORT8 0x???? /* DTC Mode Register B */
38 //#define MRB_DISELm 0x40
39 //#define MRB_CHNEm 0x80
40 //#define DTC_SAR __PORT?? 0x???? /* DTC Source Address Register */
41 //#define DTC_DAR __PORT?? 0x???? /* DTC Destination Address Register */
42 //#define DTC_CRA __PORT16 0x???? /* DTC Transfer Count Register A */
43 //#define DTC_CRB __PORT16 0x???? /* DTC Transfer Count Register B */
46 /* Module HCAN1 and HCAN2 */
47 /* Configuration registers for HCAN0 and HCAN1 */
48 #define HCAN0_MCR __PORT8 0xFFF800 /* HCAN0 Master Control Register */
49 #define HCAN1_MCR __PORT8 0xFFFA00 /* HCAN1 Master Control Register */
50 #define MCR_MCR0m 0x01
51 #define MCR_MCR1m 0x02
52 #define MCR_MCR2m 0x04
53 #define MCR_MCR5m 0x20
54 #define MCR_MCR7m 0x80
55 #define HCAN0_GSR __PORT8 0xFFF801 /* HCAN0 General Status Register */
56 #define HCAN1_GSR __PORT8 0xFFFA01 /* HCAN1 General Status Register */
57 #define GSR_GSR0m 0x01 /* Bus Off Flag */
58 #define GSR_GSR1m 0x02 /* Transmit/Receive Warning Flag */
59 #define GSR_GSR2m 0x04 /* Message Transmission Status Flag */
60 #define GSR_GSR3m 0x08 /* Reset Status Bit */
61 #define HCAN0_BCR __PORT16 0xFFF802 /* HCAN0 Bit Configuration Register */
62 #define HCAN1_BCR __PORT16 0xFFFA02 /* HCAN1 Bit Configuration Register */
63 #define BCR_BRPm 0x3f00 /* Baud Rate Prescaler (BRP) bits 8-13 */
64 #define BCR_BCR0m 0x0100 /* Baud Rate Prescaler (BRP) - bit 8 */
65 #define BCR_BCR1m 0x0200 /* Baud Rate Prescaler (BRP) - bit 9 */
66 #define BCR_BCR2m 0x0400 /* Baud Rate Prescaler (BRP) - bit 10 */
67 #define BCR_BCR3m 0x0800 /* Baud Rate Prescaler (BRP) - bit 11 */
68 #define BCR_BCR4m 0x1000 /* Baud Rate Prescaler (BRP) - bit 12 */
69 #define BCR_BCR5m 0x2000 /* Baud Rate Prescaler (BRP) - bit 13 */
70 #define BCR_SJWm 0xc000 /* Resynchronization Jump Width (SJW) */
71 #define BCR_BCR6m 0x4000 /* Resynchronization Jump Width - bit 14 */
72 #define BCR_BCR7m 0x8000 /* Resynchronization Jump Width - bit 15 */
73 #define BCR_BCR15m 0x8000 /* Bit Sample Point (BSP) */
74 #define BCR_TSEG1m 0x000f /* Time Segment 1 (TSEG1) bits 0-3 */
75 #define BCR_BCR8m 0x0001 /* Time Segment 1 (TSEG1) - bit 0 */
76 #define BCR_BCR9m 0x0002 /* Time Segment 1 (TSEG1) - bit 1 */
77 #define BCR_BCR10m 0x0004 /* Time Segment 1 (TSEG1) - bit 2 */
78 #define BCR_BCR11m 0x0008 /* Time Segment 1 (TSEG1) - bit 3 */
79 #define BCR_TSEG2m 0x0070 /* Time Segment 2 (TSEG2) bits 4-6 */
80 #define BCR_BCR12m 0x0010 /* Time Segment 2 (TSEG2) - bit 4 */
81 #define BCR_BCR13m 0x0020 /* Time Segment 2 (TSEG2) - bit 5 */
82 #define BCR_BCR14m 0x0040 /* Time Segment 2 (TSEG2) - bit 6 */
83 #define HCAN0_BCRL __PORT8 0xFFF802 /* HCAN0 Bit Configuration Register L */
84 #define HCAN1_BCRL __PORT8 0xFFFA02 /* HCAN1 Bit Configuration Register L */
85 #define BCRL_BCR0m 0x01 /* Time Segment 1 (TSEG1) bits 0-3 (BCR0-3) */
86 #define BCRL_BCR1m 0x02
87 #define BCRL_BCR2m 0x04
88 #define BCRL_BCR3m 0x08
89 #define BCRL_BCR4m 0x10 /* Time Segment 2 (TSEG2) bits 4-6 (BCR4-6) */
90 #define BCRL_BCR5m 0x20
91 #define BCRL_BCR6m 0x40
92 #define BCRL_BCR15m 0x80 /* Bit Sample Point (BSP) */
93 #define HCAN0_BCRH __PORT8 0xFFF803 /* HCAN0 Bit Configuration Register H */
94 #define HCAN1_BCRH __PORT8 0xFFFA03 /* HCAN1 Bit Configuration Register H */
95 #define BCRH_BCR0m 0x01 /* Baud Rate Prescaler (BRP) bits 8-13 */
96 #define BCRH_BCR1m 0x02
97 #define BCRH_BCR2m 0x04
98 #define BCRH_BCR3m 0x08
99 #define BCRH_BCR4m 0x10
100 #define BCRH_BCR5m 0x20
101 #define BCRH_BCR6m 0x40 /* Resynchronization Jump Width bits 14-15 */
102 #define BCRH_BCR7m 0x80
103 #define HCAN0_MBCR __PORT16 0xFFF804 /* HCAN0 Mailbox Configuration Register */
104 #define HCAN1_MBCR __PORT16 0xFFFA04 /* HCAN1 Mailbox Configuration Register */
105 #define MBCR_MBCR8m 0x0001 /* 0 = Corresponding mailbox(8) is set for transmission */
106 #define MBCR_MBCR9m 0x0002
107 #define MBCR_MBCR10m 0x0004
108 #define MBCR_MBCR11m 0x0008
109 #define MBCR_MBCR12m 0x0010
110 #define MBCR_MBCR13m 0x0020
111 #define MBCR_MBCR14m 0x0040
112 #define MBCR_MBCR15m 0x0080
113 #define MBCR_MBCR1m 0x0200
114 #define MBCR_MBCR2m 0x0400
115 #define MBCR_MBCR3m 0x0800
116 #define MBCR_MBCR4m 0x0100
117 #define MBCR_MBCR5m 0x0200
118 #define MBCR_MBCR6m 0x0400
119 #define MBCR_MBCR7m 0x0800
120 #define HCAN0_TXPR __PORT16 0xFFF806 /* HCAN0 Transmit Wait Register */
121 #define HCAN1_TXPR __PORT16 0xFFFA06 /* HCAN1 Transmit wait register */
122 #define TXPR_TXPR8m 0x0001
123 #define TXPR_TXPR9m 0x0002
124 #define TXPR_TXPR10m 0x0004
125 #define TXPR_TXPR11m 0x0008
126 #define TXPR_TXPR12m 0x0010
127 #define TXPR_TXPR13m 0x0020
128 #define TXPR_TXPR14m 0x0040
129 #define TXPR_TXPR15m 0x0080
130 #define TXPR_TXPR1m 0x0200
131 #define TXPR_TXPR2m 0x0400
132 #define TXPR_TXPR3m 0x0800
133 #define TXPR_TXPR4m 0x1000
134 #define TXPR_TXPR5m 0x2000
135 #define TXPR_TXPR6m 0x4000
136 #define TXPR_TXPR7m 0x8000
137 #define HCAN0_TXCR __PORT16 0xFFF808 /* HCAN0 Transmit wait cancel register */
138 #define HCAN1_TXCR __PORT16 0xFFFA08 /* HCAN1 Transmit wait cancel register */
139 #define TXCR_TXCR8m 0x0001
140 #define TXCR_TXCR9m 0x0002
141 #define TXCR_TXCR10m 0x0004
142 #define TXCR_TXCR11m 0x0008
143 #define TXCR_TXCR12m 0x0010
144 #define TXCR_TXCR13m 0x0020
145 #define TXCR_TXCR14m 0x0040
146 #define TXCR_TXCR15m 0x0080
147 #define TXCR_TXCR1m 0x0200
148 #define TXCR_TXCR2m 0x0400
149 #define TXCR_TXCR3m 0x0800
150 #define TXCR_TXCR4m 0x1000
151 #define TXCR_TXCR5m 0x2000
152 #define TXCR_TXCR6m 0x4000
153 #define TXCR_TXCR7m 0x8000
154 #define HCAN0_TXACK __PORT16 0xFFF80A /* HCAN0 Transmit Acknowledge Register */
155 #define HCAN1_TXACK __PORT16 0xFFFA0A /* HCAN1 Transmit Acknowledge Register */
156 #define TXACK_TXACK8m 0x0001
157 #define TXACK_TXACK9m 0x0002
158 #define TXACK_TXACK10m 0x0004
159 #define TXACK_TXACK11m 0x0008
160 #define TXACK_TXACK12m 0x0010
161 #define TXACK_TXACK13m 0x0020
162 #define TXACK_TXACK14m 0x0040
163 #define TXACK_TXACK15m 0x0080
164 #define TXACK_TXACK1m 0x0200
165 #define TXACK_TXACK2m 0x0400
166 #define TXACK_TXACK3m 0x0800
167 #define TXACK_TXACK4m 0x1000
168 #define TXACK_TXACK5m 0x2000
169 #define TXACK_TXACK6m 0x4000
170 #define TXACK_TXACK7m 0x8000
171 #define HCAN0_ABACK __PORT16 0xFFF80C /* HCAN0 Abort Acknowledge Register */
172 #define HCAN1_ABACK __PORT16 0xFFFA0C /* HCAN1 Abort Acknowledge Register */
173 #define ABACK_ABACK8m 0x0001
174 #define ABACK_ABACK9m 0x0002
175 #define ABACK_ABACK10m 0x0004
176 #define ABACK_ABACK11m 0x0008
177 #define ABACK_ABACK12m 0x0010
178 #define ABACK_ABACK13m 0x0020
179 #define ABACK_ABACK14m 0x0040
180 #define ABACK_ABACK15m 0x0080
181 #define ABACK_ABACK1m 0x0200
182 #define ABACK_ABACK2m 0x0400
183 #define ABACK_ABACK3m 0x0800
184 #define ABACK_ABACK4m 0x1000
185 #define ABACK_ABACK5m 0x2000
186 #define ABACK_ABACK6m 0x4000
187 #define ABACK_ABACK7m 0x8000
188 #define HCAN0_RXPR __PORT16 0xFFF80E /* HCAN0 Receive Complete Register */
189 #define HCAN1_RXPR __PORT16 0xFFFA0E /* HCAN1 Receive Complete Register */
190 #define RXPR_RXPR8m 0x0001
191 #define RXPR_RXPR9m 0x0002
192 #define RXPR_RXPR10m 0x0004
193 #define RXPR_RXPR11m 0x0008
194 #define RXPR_RXPR12m 0x0010
195 #define RXPR_RXPR13m 0x0020
196 #define RXPR_RXPR14m 0x0040
197 #define RXPR_RXPR15m 0x0080
198 #define RXPR_RXPR0m 0x0100
199 #define RXPR_RXPR1m 0x0200
200 #define RXPR_RXPR2m 0x0400
201 #define RXPR_RXPR3m 0x0800
202 #define RXPR_RXPR4m 0x1000
203 #define RXPR_RXPR5m 0x2000
204 #define RXPR_RXPR6m 0x4000
205 #define RXPR_RXPR7m 0x8000
206 #define HCAN0_RFPR __PORT16 0xFFF810 /* HCAN0 Remote Request Register */
207 #define HCAN1_RFPR __PORT16 0xFFFA10 /* HCAN1 Remote Request Register */
208 #define RFPR_RFPR8m 0x0001
209 #define RFPR_RFPR9m 0x0002
210 #define RFPR_RFPR10m 0x0004
211 #define RFPR_RFPR11m 0x0008
212 #define RFPR_RFPR12m 0x0010
213 #define RFPR_RFPR13m 0x0020
214 #define RFPR_RFPR14m 0x0040
215 #define RFPR_RFPR15m 0x0080
216 #define RFPR_RFPR0m 0x0100
217 #define RFPR_RFPR1m 0x0200
218 #define RFPR_RFPR2m 0x0400
219 #define RFPR_RFPR3m 0x0800
220 #define RFPR_RFPR4m 0x1000
221 #define RFPR_RFPR5m 0x2000
222 #define RFPR_RFPR6m 0x4000
223 #define RFPR_RFPR7m 0x8000
224 #define HCAN0_IRR __PORT16 0xFFF812 /* HCAN0 Interrupt Register */
225 #define HCAN1_IRR __PORT16 0xFFFA12 /* HCAN1 Interrupt Register */
226 #define IRR_IRR0m 0x0100
227 #define IRR_IRR1m 0x0200
228 #define IRR_IRR2m 0x0400
229 #define IRR_IRR3m 0x0800
230 #define IRR_IRR4m 0x1000
231 #define IRR_IRR5m 0x2000
232 #define IRR_IRR6m 0x4000
233 #define IRR_IRR7m 0x8000
234 #define IRR_IRR8m 0x0001
235 #define IRR_IRR9m 0x0002
236 #define IRR_IRR12m 0x0010
237 #define HCAN0_IRRL __PORT8 0xFFF812 /* HCAN0 Interrupt Register L */
238 #define HCAN1_IRRL __PORT8 0xFFFA12 /* HCAN1 Interrupt Register L */
239 #define IRRL_IRR0m 0x01
240 #define IRRL_IRR1m 0x02
241 #define IRRL_IRR2m 0x04
242 #define IRRL_IRR3m 0x08
243 #define IRRL_IRR4m 0x10
244 #define IRRL_IRR5m 0x20
245 #define IRRL_IRR6m 0x40
246 #define IRRL_IRR7m 0x80
247 #define HCAN0_IRRH __PORT8 0xFFF813 /* HCAN0 Interrupt Register H */
248 #define HCAN1_IRRH __PORT8 0xFFFA13 /* HCAN0 Interrupt Register H */
249 #define IRRH_IRR8m 0x01
250 #define IRRH_IRR9m 0x02
251 #define IRRH_IRR12m 0x10
252 #define HCAN0_MBIMR __PORT16 0xFFF814 /* HCAN0 Mailbox Interrupt Mask Register */
253 #define HCAN1_MBIMR __PORT16 0xFFFA14 /* HCAN1 Mailbox Interrupt Mask Register */
254 #define MBIMR_MBIMR8m 0x0001
255 #define MBIMR_MBIMR9m 0x0002
256 #define MBIMR_MBIMR10m 0x0004
257 #define MBIMR_MBIMR11m 0x0008
258 #define MBIMR_MBIMR12m 0x0010
259 #define MBIMR_MBIMR13m 0x0020
260 #define MBIMR_MBIMR14m 0x0040
261 #define MBIMR_MBIMR15m 0x0080
262 #define MBIMR_MBIMR0m 0x0100
263 #define MBIMR_MBIMR1m 0x0200
264 #define MBIMR_MBIMR2m 0x0400
265 #define MBIMR_MBIMR3m 0x0800
266 #define MBIMR_MBIMR4m 0x1000
267 #define MBIMR_MBIMR5m 0x2000
268 #define MBIMR_MBIMR6m 0x4000
269 #define MBIMR_MBIMR7m 0x8000
270 #define HCAN0_IMR __PORT16 0xFFF816 /* HCAN0 Interrupt Mask Register */
271 #define HCAN1_IMR __PORT16 0xFFFA16 /* HCAN1 Interrupt Mask Register */
272 #define IMR_IMR8m 0x0001
273 #define IMR_IMR9m 0x0002
274 #define IMR_IMR12m 0x0010
275 #define IMR_IMR1m 0x0200
276 #define IMR_IMR2m 0x0400
277 #define IMR_IMR3m 0x0800
278 #define IMR_IMR4m 0x1000
279 #define IMR_IMR5m 0x2000
280 #define IMR_IMR6m 0x4000
281 #define IMR_IMR7m 0x8000
282 #define HCAN0_IMRL __PORT8 0xFFF816 /* HCAN0 Interrupt Mask Register L */
283 #define HCAN1_IMRL __PORT8 0xFFFA16 /* HCAN1 Interrupt Mask Register L */
284 #define IMRL_IMR1m 0x02
285 #define IMRL_IMR2m 0x04
286 #define IMRL_IMR3m 0x08
287 #define IMRL_IMR4m 0x10
288 #define IMRL_IMR5m 0x20
289 #define IMRL_IMR6m 0x40
290 #define IMRL_IMR7m 0x80
291 #define HCAN0_IMRH __PORT8 0xFFF817 /* HCAN0 Interrupt Mask Register H */
292 #define HCAN1_IMRH __PORT8 0xFFFA17 /* HCAN1 Interrupt Mask Register H */
293 #define IMRH_IMR8m 0x01
294 #define IMRH_IMR9m 0x02
295 #define IMRH_IMR12m 0x10
296 #define HCAN0_REC __PORT8 0xFFF818 /* HCAN0 Receive Error Counter */
297 #define HCAN1_REC __PORT8 0xFFFA18 /* HCAN1 Receive Error Counter */
298 #define HCAN0_TEC __PORT8 0xFFF819 /* HCAN0 Transmit Error Counter */
299 #define HCAN1_TEC __PORT8 0xFFFA19 /* HCAN1 Transmit Error Counter */
300 #define HCAN0_UMSR __PORT16 0xFFF81A /* HCAN0 Unread Message Status Register */
301 #define HCAN1_UMSR __PORT16 0xFFFA1A /* HCAN1 Unread Message Status Register */
302 #define UMSR_UMSR8m 0x0001
303 #define UMSR_UMSR9m 0x0002
304 #define UMSR_UMSR10m 0x0004
305 #define UMSR_UMSR11m 0x0008
306 #define UMSR_UMSR12m 0x0010
307 #define UMSR_UMSR13m 0x0020
308 #define UMSR_UMSR14m 0x0040
309 #define UMSR_UMSR15m 0x0080
310 #define UMSR_UMSR0m 0x0100
311 #define UMSR_UMSR1m 0x0200
312 #define UMSR_UMSR2m 0x0400
313 #define UMSR_UMSR3m 0x0800
314 #define UMSR_UMSR4m 0x1000
315 #define UMSR_UMSR5m 0x2000
316 #define UMSR_UMSR6m 0x4000
317 #define UMSR_UMSR7m 0x8000
318 #define HCAN0_LAFML __PORT16 0xFFF81C /* HCAN0 Local Acceptance Filter Masks L */
319 #define HCAN1_LAFML __PORT16 0xFFFA1C /* HCAN1 Local Acceptance Filter Masks L */
320 #define HCAN0_LAFMH __PORT16 0xFFF81E /* HCAN0 Local Acceptance Filter Masks H */
321 #define HCAN1_LAFMH __PORT16 0xFFFA1E /* HCAN1 Local Acceptance Filter Masks H */
322 /* Message Control and Data registers (MC0 to MC15) and (MD0 to MD15) for HCAN0 and HCAN1 */
323 #define HCAN0_MC0 __PORT16 0xFFF820 /* Message Control 0 */
324 #define HCAN1_MC0 __PORT16 0xFFFA20
325 #define HCAN0_MC1 __PORT16 0xFFF828 /* Message Control 1 */
326 #define HCAN1_MC1 __PORT16 0xFFFA28
327 #define HCAN0_MC2 __PORT16 0xFFF830 /* Message Control 2 */
328 #define HCAN1_MC2 __PORT16 0xFFFA30
329 #define HCAN0_MC3 __PORT16 0xFFF838 /* Message Control 3 */
330 #define HCAN1_MC3 __PORT16 0xFFFA38
331 #define HCAN0_MC4 __PORT16 0xFFF840 /* Message Control 4 */
332 #define HCAN1_MC4 __PORT16 0xFFFA40
333 #define HCAN0_MC5 __PORT16 0xFFF848 /* Message Control 5 */
334 #define HCAN1_MC5 __PORT16 0xFFFA48
335 #define HCAN0_MC6 __PORT16 0xFFF850 /* Message Control 6 */
336 #define HCAN1_MC6 __PORT16 0xFFFA50
337 #define HCAN0_MC7 __PORT16 0xFFF858 /* Message Control 7 */
338 #define HCAN1_MC7 __PORT16 0xFFFA58
339 #define HCAN0_MC8 __PORT16 0xFFF860 /* Message Control 8 */
340 #define HCAN1_MC8 __PORT16 0xFFFA60
341 #define HCAN0_MC9 __PORT16 0xFFF868 /* Message Control 9 */
342 #define HCAN1_MC9 __PORT16 0xFFFA68
343 #define HCAN0_MC10 __PORT16 0xFFF870 /* Message Control 10 */
344 #define HCAN1_MC10 __PORT16 0xFFFA70
345 #define HCAN0_MC11 __PORT16 0xFFF878 /* Message Control 11 */
346 #define HCAN1_MC11 __PORT16 0xFFFA78
347 #define HCAN0_MC12 __PORT16 0xFFF880 /* Message Control 12 */
348 #define HCAN1_MC12 __PORT16 0xFFFA80
349 #define HCAN0_MC13 __PORT16 0xFFF888 /* Message Control 13 */
350 #define HCAN1_MC13 __PORT16 0xFFFA88
351 #define HCAN0_MC14 __PORT16 0xFFF890 /* Message Control 14 */
352 #define HCAN1_MC14 __PORT16 0xFFFA90
353 #define HCAN0_MC15 __PORT16 0xFFF898 /* Message Control 15 */
354 #define HCAN1_MC15 __PORT16 0xFFFA98
355 #define HCAN0_MD0 __PORT16 0xFFF8B0 /* Message Data 0 */
356 #define HCAN1_MD0 __PORT16 0xFFFAB0
357 #define HCAN0_MD1 __PORT16 0xFFF8B8 /* Message Data 1 */
358 #define HCAN1_MD1 __PORT16 0xFFFAB8
359 #define HCAN0_MD2 __PORT16 0xFFF8C0 /* Message Data 2 */
360 #define HCAN1_MD2 __PORT16 0xFFFAC0
361 #define HCAN0_MD3 __PORT16 0xFFF8C8 /* Message Data 3 */
362 #define HCAN1_MD3 __PORT16 0xFFFAC8
363 #define HCAN0_MD4 __PORT16 0xFFF8D0 /* Message Data 4 */
364 #define HCAN1_MD4 __PORT16 0xFFFAD0
365 #define HCAN0_MD5 __PORT16 0xFFF8D8 /* Message Data 5 */
366 #define HCAN1_MD5 __PORT16 0xFFFAD8
367 #define HCAN0_MD6 __PORT16 0xFFF8E0 /* Message Data 6 */
368 #define HCAN1_MD6 __PORT16 0xFFFAE0
369 #define HCAN0_MD7 __PORT16 0xFFF8E8 /* Message Data 7 */
370 #define HCAN1_MD7 __PORT16 0xFFFAE8
371 #define HCAN0_MD8 __PORT16 0xFFF8F0 /* Message Data 8 */
372 #define HCAN1_MD8 __PORT16 0xFFFAF0
373 #define HCAN0_MD9 __PORT16 0xFFF8F8 /* Message Data 9 */
374 #define HCAN1_MD9 __PORT16 0xFFFAF8
375 #define HCAN0_MD10 __PORT16 0xFFF900 /* Message Data 10 */
376 #define HCAN1_MD10 __PORT16 0xFFFB00
377 #define HCAN0_MD11 __PORT16 0xFFF908 /* Message Data 11 */
378 #define HCAN1_MD11 __PORT16 0xFFFB08
379 #define HCAN0_MD12 __PORT16 0xFFF910 /* Message Data 12 */
380 #define HCAN1_MD12 __PORT16 0xFFFB10
381 #define HCAN0_MD13 __PORT16 0xFFF918 /* Message Data 13 */
382 #define HCAN1_MD13 __PORT16 0xFFFB18
383 #define HCAN0_MD14 __PORT16 0xFFF920 /* Message Data 14 */
384 #define HCAN1_MD14 __PORT16 0xFFFB20
385 #define HCAN0_MD15 __PORT16 0xFFF928 /* Message Data 15 */
386 #define HCAN1_MD15 __PORT16 0xFFFB28
388 /* Motor control PWM timer 1 */
389 #define PWM_PWCR1 __PORT8 0xFFFC00 /* PWM control register 1 */
390 #define PWCR1_CKS0m 0x01
391 #define PWCR1_CKS1m 0x02
392 #define PWCR1_CKS2m 0x04
393 #define PWCR1_CSTm 0x08
394 #define PWCR1_CMFm 0x10
395 #define PWCR1_IEm 0x20
396 #define PWM_PWOCR1 __PORT8 0xFFFC02 /* PWM Output Control Register 1 */
397 #define PWOCR1_OE1Am 0x01
398 #define PWOCR1_OE1Bm 0x02
399 #define PWOCR1_OE1Cm 0x04
400 #define PWOCR1_OE1Dm 0x08
401 #define PWOCR1_OE1Em 0x10
402 #define PWOCR1_OE1Fm 0x20
403 #define PWOCR1_OE1Gm 0x40
404 #define PWOCR1_OE1Hm 0x80
405 #define PWM_PWPR1 __PORT8 0xFFFC04 /* PWM Polarity Register 1 */
406 #define PWPR1_OPS1Am 0x01
407 #define PWPR1_OPS1Bm 0x02
408 #define PWPR1_OPS1Cm 0x04
409 #define PWPR1_OPS1Dm 0x08
410 #define PWPR1_OPS1Em 0x10
411 #define PWPR1_OPS1Fm 0x20
412 #define PWPR1_OPS1Gm 0x40
413 #define PWPR1_OPS1Hm 0x80
414 #define PWM_PWCYR1 __PORT16 0xFFFC06 /* PWM Cycle Register 1 */
415 #define PWM_PWBFR1A __PORT16 0xFFFC08 /* PWM Buffer Register 1A */
416 #define PWBFR1A_DT8m 0x0100
417 #define PWBFR1A_DT9m 0x0200
418 #define PWBFR1A_OTSm 0x1000
419 #define PWM_PWBFR1C __PORT16 0xFFFC0A /* PWM Buffer Register 1C */
420 #define PWBFR1C_DT8m 0x0100
421 #define PWBFR1C_DT9m 0x0200
422 #define PWBFR1C_OTSm 0x1000
423 #define PWM_PWBFR1E __PORT16 0xFFFC0C /* PWM Buffer Register 1E */
424 #define PWBFR1E_DT8m 0x0100
425 #define PWBFR1E_DT9m 0x0200
426 #define PWBFR1E_OTSm 0x1000
427 #define PWM_PWBFR1G __PORT16 0xFFFC0E /* PWM Buffer Register 1G */
428 #define PWBFR1G_DT8m 0x0100
429 #define PWBFR1G_DT9m 0x0200
430 #define PWBFR1G_OTSm 0x1000
431 /* Motor control PWM timer 2 */
432 #define PWM_PWCR2 __PORT8 0xFFFC10 /* PWM Control Register 2 */
433 #define PWCR2_CKS0m 0x01
434 #define PWCR2_CKS1m 0x02
435 #define PWCR2_CKS2m 0x04
436 #define PWCR2_CSTm 0x08
437 #define PWCR2_CMFm 0x10
438 #define PWCR2_IEm 0x20
439 #define PWM_PWOCR2 __PORT8 0xFFFC12 /* PWM Output Control Register 2 */
440 #define PWOCR2_OE2Am 0x01
441 #define PWOCR2_OE2Bm 0x02
442 #define PWOCR2_OE2Cm 0x04
443 #define PWOCR2_OE2Dm 0x08
444 #define PWOCR2_OE2Em 0x10
445 #define PWOCR2_OE2Fm 0x20
446 #define PWOCR2_OE2Gm 0x40
447 #define PWOCR2_OE2Hm 0x80
448 #define PWM_PWPR2 __PORT8 0xFFFC14 /* PWM Polarity Register 2 */
449 #define PWPR2_OPS2Am 0x01
450 #define PWPR2_OPS2Bm 0x02
451 #define PWPR2_OPS2Cm 0x04
452 #define PWPR2_OPS2Dm 0x08
453 #define PWPR2_OPS2Em 0x10
454 #define PWPR2_OPS2Fm 0x20
455 #define PWPR2_OPS2Gm 0x40
456 #define PWPR2_OPS2Hm 0x80
457 #define PWM_PWCYR2 __PORT16 0xFFFC16 /* PWM Cycle Register 2 */
458 #define PWM_PWBFR2A __PORT16 0xFFFC18 /* PWM Buffer Register 2A */
459 #define PWBFR2A_DT8m 0x0100
460 #define PWBFR2A_DT9m 0x0200
461 #define PWBFR2A_TDSm 0x1000
462 #define PWM_PWBFR2B __PORT16 0xFFFC1A /* PWM Buffer Register 2B */
463 #define PWBFR2B_DT8m 0x0100
464 #define PWBFR2B_DT9m 0x0200
465 #define PWBFR2B_TDSm 0x1000
466 #define PWM_PWBFR2C __PORT16 0xFFFC1C /* PWM Buffer Register 2C */
467 #define PWBFR2C_DT8m 0x0100
468 #define PWBFR2C_DT9m 0x0200
469 #define PWBFR2C_TDSm 0x1000
470 #define PWM_PWBFR2D __PORT16 0xFFFC1E /* PWM Buffer Register 2E */
471 #define PWBFR2D_DT8m 0x0100
472 #define PWBFR2D_DT9m 0x0200
473 #define PWBFR2D_TDSm 0x1000
474 /* Port H and J Registers */
475 #define DIO_PHDDR __PORT8 0xFFFC20 /* DIO H Data Direction Register */
476 #define PHDDR_PH0DDRm 0x01
477 #define PHDDR_PH1DDRm 0x02
478 #define PHDDR_PH2DDRm 0x04
479 #define PHDDR_PH3DDRm 0x08
480 #define PHDDR_PH4DDRm 0x10
481 #define PHDDR_PH5DDRm 0x20
482 #define PHDDR_PH6DDRm 0x40
483 #define PHDDR_PH7DDRm 0x80
484 #define DIO_PJDDR __PORT8 0xFFFC21 /* DIO J Data Direction Register */
485 #define PJDDR_PJ0DDRm 0x01
486 #define PJDDR_PJ1DDRm 0x02
487 #define PJDDR_PJ2DDRm 0x04
488 #define PJDDR_PJ3DDRm 0x08
489 #define PJDDR_PJ4DDRm 0x10
490 #define PJDDR_PJ5DDRm 0x20
491 #define PJDDR_PJ6DDRm 0x40
492 #define PJDDR_PJ7DDRm 0x80
493 #define DIO_PHDR __PORT8 0xFFFC24 /* DIO H Data Register */
494 #define PHDR_PH0DRm 0x01
495 #define PHDR_PH1DRm 0x02
496 #define PHDR_PH2DRm 0x04
497 #define PHDR_PH3DRm 0x08
498 #define PHDR_PH4DRm 0x10
499 #define PHDR_PH5DRm 0x20
500 #define PHDR_PH6DRm 0x40
501 #define PHDR_PH7DRm 0x80
502 #define DIO_PJDR __PORT8 0xFFFC25 /* DIO J Data Register */
503 #define PJDR_PJ0DRm 0x01
504 #define PJDR_PJ1DRm 0x02
505 #define PJDR_PJ2DRm 0x04
506 #define PJDR_PJ3DRm 0x08
507 #define PJDR_PJ4DRm 0x10
508 #define PJDR_PJ5DRm 0x20
509 #define PJDR_PJ6DRm 0x40
510 #define PJDR_PJ7DRm 0x80
511 #define DIO_PORTH __PORT8 0xFFFC28 /* DIO H Register */
512 #define PORTH_PH0m 0x01
513 #define PORTH_PH1m 0x02
514 #define PORTH_PH2m 0x04
515 #define PORTH_PH3m 0x08
516 #define PORTH_PH4m 0x10
517 #define PORTH_PH5m 0x20
518 #define PORTH_PH6m 0x40
519 #define PORTH_PH7m 0x80
520 #define DIO_PORTJ __PORT8 0xFFFC29 /* DIO J Register */
521 #define PORTJ_PJ0m 0x01
522 #define PORTJ_PJ1m 0x02
523 #define PORTJ_PJ2m 0x04
524 #define PORTJ_PJ3m 0x08
525 #define PORTJ_PJ4m 0x10
526 #define PORTJ_PJ5m 0x20
527 #define PORTJ_PJ6m 0x40
528 #define PORTJ_PJ7m 0x80
530 /* Module IIC valid in 2630,2638 and 2639 */
531 #define IIC_SCRX __PORT8 0xFFFDB4 /* Serial Control Register X */
532 #define SCRX_IICEm 0x10
533 #define SCRX_IICX0m 0x20
534 #define SCRX_IICX1m 0x40
535 #define IIC_DDCSWR __PORT8 0xFFFDB5 /* DDC Switch Register */
536 #define DDCSWR_CLR0m 0x01
537 #define DDCSWR_CLR1m 0x02
538 #define DDCSWR_CLR2m 0x04
539 #define DDCSWR_CLR3m 0x08
540 #define DDCSWR_IFm 0x10
541 #define DDCSWR_IEm 0x20
542 #define DDCSWR_SWm 0x40
543 #define DDCSWR_SWEm 0x80
545 #define SYS_SBYCR __PORT8 0xFFFDE4 /* Standby Control Register */
546 #define SBYCR_OPEm 0x08
547 #define SBYCR_STS0m 0x10
548 #define SBYCR_STS1m 0x20
549 #define SBYCR_STS2m 0x40
550 #define SBYCR_SSBYm 0x80
551 #define SYS_SYSCR __PORT8 0xFFFDE5 /* SYS Control Register */
552 #define SYSCR_RAMEm 0x01
553 #define SYSCR_NMIEGm 0x08
554 #define SYSCR_INTM0m 0x10
555 #define SYSCR_INTM1m 0x20
556 #define SYSCR_MACSm 0x80
557 #define SYS_SCKCR __PORT8 0xFFFDE6 /* SYS Clock Control Register */
558 #define SCKCR_SCK0m 0x01 /* Bus master clock selection */
559 #define SCKCR_SCK1m 0x02 /* 0=full, 1=/2, 2=/4 3=/8 */
560 #define SCKCR_SCK2m 0x04 /* 4=/16, 5=/32 */
561 #define SCKCR_SCKxm 0x07
562 #define SCKCR_STCSm 0x08 /* 1=Immediately change, 0=at Stby */
563 #define SCKCR_PSTOPm 0x80 /* 1=Clock Output Disable */
564 #define SYS_MDCR __PORT8 0xFFFDE7 /* Mode Control Register */
565 #define MDCR_MDS0m 0x01
566 #define MDCR_MDS1m 0x02
567 #define MDCR_MDS2m 0x04
568 #define SYS_PFCR __PORT8 0xFFFDEB /* Pin Function Control Register */
569 #define PFCR_AE0m 0x01
570 #define PFCR_AE1m 0x02
571 #define PFCR_AE2m 0x04
572 #define PFCR_AE3m 0x08
573 #define PFCR_AExm 0x0f
574 #define SYS_LPWRCR __PORT8 0xFFFDEC /* Low-Power Control Register */
575 #define LPWRCR_STC0m 0x01
576 #define LPWRCR_STC1m 0x02
577 #define LPWRCR_STCxm 0x03
578 #define LPWRCR_RFCUTm 0x08
579 #define LPWRCR_SUBSTPm 0x10
580 #define LPWRCR_NESELm 0x20
581 #define LPWRCR_LSONm 0x40
582 #define LPWRCR_DTONm 0x80
583 /* Module PC Break Controller */
584 #define PBC_BARA __PORT32 0xFFFE00 /* Break Address Register A */
585 #define PBC_BARB __PORT32 0xFFFE04 /* Break Address Register B */
586 #define PBC_BCRA __PORT8 0xFFFE08 /* Break Control Register A */
587 #define BCRA_BIEAm 0x01
588 #define BCRA_CSELA0m 0x02
589 #define BCRA_CSELA1m 0x04
590 #define BCRA_BAMRA0m 0x08
591 #define BCRA_BAMRA1m 0x10
592 #define BCRA_BAMRA2m 0x20
593 #define BCRA_CDAm 0x40
594 #define BCRA_CMFAm 0x80
595 #define PBC_BCRB __PORT8 0xFFFE09 /* Break Control Register B */
596 #define BCRB_BIEAm 0x01
597 #define BCRB_CSELA0m 0x02
598 #define BCRB_CSELA1m 0x04
599 #define BCRB_BAMRA0m 0x08
600 #define BCRB_BAMRA1m 0x10
601 #define BCRB_BAMRA2m 0x20
602 #define BCRB_CDAm 0x40
603 #define BCRB_CMFAm 0x80
604 /* Module Interrupt Controller Registers */
605 #define INT_ISCRH __PORT8 0xFFFE12 /* IRQ Sence Control Register H */
606 #define ISCRH_IRQ4SCAm 0x01
607 #define ISCRH_IRQ4SCBm 0x02
608 #define ISCRH_IRQ5SCAm 0x04
609 #define ISCRH_IRQ5SCBm 0x08
610 #define INT_ISCRL __PORT8 0xFFFE13 /* IRQ Sence Control Register L */
611 #define ISCRL_IRQ0SCAm 0x01
612 #define ISCRL_IRQ0SCBm 0x02
613 #define ISCRL_IRQ1SCAm 0x04
614 #define ISCRL_IRQ1SCBm 0x08
615 #define ISCRL_IRQ2SCAm 0x10
616 #define ISCRL_IRQ2SCBm 0x20
617 #define ISCRL_IRQ3SCAm 0x40
618 #define ISCRL_IRQ3SCBm 0x80
619 #define INT_IER __PORT8 0xFFFE14 /* IRQ Enable Register */
620 #define IER_IRQ0Em 0x01
621 #define IER_IRQ1Em 0x02
622 #define IER_IRQ2Em 0x04
623 #define IER_IRQ3Em 0x08
624 #define IER_IRQ4Em 0x10
625 #define IER_IRQ5Em 0x20
626 #define INT_ISR __PORT8 0xFFFE15 /* IRQ Status Register */
627 #define ISR_IRQ0Fm 0x01
628 #define ISR_IRQ1Fm 0x02
629 #define ISR_IRQ2Fm 0x04
630 #define ISR_IRQ3Fm 0x08
631 #define ISR_IRQ4Fm 0x10
632 #define ISR_IRQ5Fm 0x20
634 #define DTC_DTCERA __PORT8 0xFFFE16 /* DTC Enable Register A */
635 #define DTCERA_DTCEA0m 0x01
636 #define DTCERA_DTCEA1m 0x02
637 #define DTCERA_DTCEA2m 0x04
638 #define DTCERA_DTCEA3m 0x08
639 #define DTCERA_DTCEA4m 0x10
640 #define DTCERA_DTCEA5m 0x20
641 #define DTCERA_DTCEA6m 0x40
642 #define DTCERA_DTCEA7m 0x80
643 #define DTC_DTCERB __PORT8 0xFFFE17 /* DTC Enable Register B */
644 #define DTCERB_DTCEB0m 0x01
645 #define DTCERB_DTCEB1m 0x02
646 #define DTCERB_DTCEB2m 0x04
647 #define DTCERB_DTCEB3m 0x08
648 #define DTCERB_DTCEB4m 0x10
649 #define DTCERB_DTCEB5m 0x20
650 #define DTCERB_DTCEB6m 0x40
651 #define DTCERB_DTCEB7m 0x80
652 #define DTC_DTCERC __PORT8 0xFFFE18 /* DTC Enable Register C */
653 #define DTCERC_DTCEC0m 0x01
654 #define DTCERC_DTCEC1m 0x02
655 #define DTCERC_DTCEC2m 0x04
656 #define DTCERC_DTCEC3m 0x08
657 #define DTCERC_DTCEC4m 0x10
658 #define DTCERC_DTCEC5m 0x20
659 #define DTCERC_DTCEC6m 0x40
660 #define DTCERC_DTCEC7m 0x80
661 #define DTC_DTCERD __PORT8 0xFFFE19 /* DTC Enable Register D */
662 #define DTCERD_DTCED0m 0x01
663 #define DTCERD_DTCED1m 0x02
664 #define DTCERD_DTCED2m 0x04
665 #define DTCERD_DTCED3m 0x08
666 #define DTCERD_DTCED4m 0x10
667 #define DTCERD_DTCED5m 0x20
668 #define DTCERD_DTCED6m 0x40
669 #define DTCERD_DTCED7m 0x80
670 #define DTC_DTCERE __PORT8 0xFFFE1A /* DTC Enable Register E */
671 #define DTCERE_DTCEE0m 0x01
672 #define DTCERE_DTCEE1m 0x02
673 #define DTCERE_DTCEE2m 0x04
674 #define DTCERE_DTCEE3m 0x08
675 #define DTCERE_DTCEE4m 0x10
676 #define DTCERE_DTCEE5m 0x20
677 #define DTCERE_DTCEE6m 0x40
678 #define DTCERE_DTCEE7m 0x80
679 #define DTC_DTCERF __PORT8 0xFFFE1B /* DTC Enable Register F */
680 #define DTCERF_DTCEF0m 0x01
681 #define DTCERF_DTCEF1m 0x02
682 #define DTCERF_DTCEF2m 0x04
683 #define DTCERF_DTCEF3m 0x08
684 #define DTCERF_DTCEF4m 0x10
685 #define DTCERF_DTCEF5m 0x20
686 #define DTCERF_DTCEF6m 0x40
687 #define DTCERF_DTCEF7m 0x80
688 #define DTC_DTCERG __PORT8 0xFFFE1C /* DTC Enable Register G */
689 #define DTCERG_DTCEG0m 0x01
690 #define DTCERG_DTCEG1m 0x02
691 #define DTCERG_DTCEG2m 0x04
692 #define DTCERG_DTCEG3m 0x08
693 #define DTCERG_DTCEG4m 0x10
694 #define DTCERG_DTCEG5m 0x20
695 #define DTCERG_DTCEG6m 0x40
696 #define DTCERG_DTCEG7m 0x80
697 #define DTC_DTVECR __PORT8 0xFFFE1F /* DTC Vector Register */
698 #define DTVECR_DTVEC0m 0x01
699 #define DTVECR_DTVEC1m 0x02
700 #define DTVECR_DTVEC2m 0x04
701 #define DTVECR_DTVEC3m 0x08
702 #define DTVECR_DTVEC4m 0x10
703 #define DTVECR_DTVEC5m 0x20
704 #define DTVECR_DTVEC6m 0x40
705 #define DTVECR_SWDTEm 0x80
706 /* Module Programmable Pulse Generator */
707 #define PPG_PCR __PORT8 0xFFFE26 /* PPG Output Control Register */
708 #define PCR_G0CMS0m 0x01
709 #define PCR_G0CMS1m 0x02
710 #define PCR_G1CMS0m 0x04
711 #define PCR_G1CMS1m 0x08
712 #define PCR_G2CMS0m 0x10
713 #define PCR_G2CMS1m 0x20
714 #define PCR_G3CMS0m 0x40
715 #define PCR_G3CMS1m 0x80
716 #define PPG_PMR __PORT8 0xFFFE27 /* PPG Output Mode Register */
717 #define PMR_G0NOVm 0x01
718 #define PMR_G1NOVm 0x02
719 #define PMR_G2NOVm 0x04
720 #define PMR_G3INVm 0x08
721 #define PMR_G0INVm 0x10
722 #define PMR_G1INVm 0x20
723 #define PMR_G2INVm 0x40
724 #define PMM_G3INVm 0x80
725 #define PPG_NDERH __PORT8 0xFFFE28 /* Next Data Enable Register H */
726 #define NDERH_NDER8m 0x01
727 #define NDERH_NDER9m 0x02
728 #define NDERH_NDER10m 0x04
729 #define NDERH_NDER11m 0x08
730 #define NDERH_NDER12m 0x10
731 #define NDERH_NDER13m 0x20
732 #define NDERH_NDER14m 0x40
733 #define NDERH_NDER15m 0x80
734 #define PPG_NDERL __PORT8 0xFFFE29 /* Next Data Enable Register L */
735 #define NDERL_NDER0m 0x01
736 #define NDERL_NDER1m 0x02
737 #define NDERL_NDER2m 0x04
738 #define NDERL_NDER3m 0x08
739 #define NDERL_NDER4m 0x10
740 #define NDERL_NDER5m 0x20
741 #define NDERL_NDER6m 0x40
742 #define NDERL_NDER7m 0x80
743 #define PPG_PODRH __PORT8 0xFFFE2A /* Output Data Register H */
744 #define PODRH_POD8m 0x01
745 #define PODRH_POD9m 0x02
746 #define PODRH_POD10m 0x04
747 #define PODRH_POD11m 0x08
748 #define PODRH_POD12m 0x10
749 #define PODRH_POD13m 0x20
750 #define PODRH_POD14m 0x40
751 #define PODRH_POD15m 0x80
752 #define PPG_PODRL __PORT8 0xFFFE2B /* Output Data Register L */
753 #define PODRL_POD0m 0x01
754 #define PODRL_POD1m 0x02
755 #define PODRL_POD2m 0x04
756 #define PODRL_POD3m 0x08
757 #define PODRL_POD4m 0x10
758 #define PODRL_POD5m 0x20
759 #define PODRL_POD6m 0x40
760 #define PODRL_POD7m 0x80
761 //#define PPG_NDRH __PORT8 0xFFFE2C /* Next data register H */ /* Use when group2 and group3 have the same output trigger selected */
762 #define NDRH_NDR8m 0x01 /* Use for group2 if group3 have different output triger to group2 */
763 #define NDRH_NDR9m 0x02
764 #define NDRH_NDR10m 0x04
765 #define NDRH_NDR11m 0x08
766 #define NDRH_NDR12m 0x10
767 #define NDRH_NDR13m 0x20
768 #define NDRH_NDR14m 0x40
769 #define NDRH_NDR15m 0x80
770 //#define PPG_NDRL __PORT8 0xFFFE2D /* Next data register L */ /* Use when group2 and group3 have the same output trigger selected */
771 #define NDRL_NDR0m 0x01 /* Use for group2 if group3 have different output triger to group2 */
772 #define NDRL_NDR1m 0x02
773 #define NDRL_NDR2m 0x04
774 #define NDRL_NDR3m 0x08
775 #define NDRL_NDR4m 0x10
776 #define NDRL_NDR5m 0x20
777 #define NDRL_NDR6m 0x40
778 #define NDRL_NDR7m 0x80
779 //#define PPG_NDRH __PORT8 0xFFFE2E /* Next Data Register H */ /* Use for group3 if group2 and group3 have different triggers */
780 #define NDRH_NDR8m 0x01
781 #define NDRH_NDR9m 0x02
782 #define NDRH_NDR10m 0x04
783 #define NDRH_NDR11m 0x08
784 //#define PPG_NDRL __PORT8 0xFFFE2F /* Next Data Register L */ /* Use for group3 if group2 and group3 have different triggers */
785 #define NDRL_NDR0m 0x01
786 #define NDRL_NDR1m 0x02
787 #define NDRL_NDR2m 0x04
788 #define NDRL_NDR3m 0x08
790 #define DIO_P1DDR __PORT8 0xFFFE30 /* DIO 1 Data Direction Register */
791 #define P1DDR_P10DDRm 0x01
792 #define P1DDR_P11DDRm 0x02
793 #define P1DDR_P12DDRm 0x04
794 #define P1DDR_P13DDRm 0x08
795 #define P1DDR_P14DDRm 0x10
796 #define P1DDR_P15DDRm 0x20
797 #define P1DDR_P16DDRm 0x40
798 #define P1DDR_P17DDRm 0x80
799 #define DIO_P3DDR __PORT8 0xFFFE32 /* DIO 3 Data Direction Register */
800 #define P3DDR_P30DDRm 0x01
801 #define P3DDR_P31DDRm 0x02
802 #define P3DDR_P32DDRm 0x04
803 #define P3DDR_P33DDRm 0x08
804 #define P3DDR_P34DDRm 0x10
805 #define P3DDR_P35DDRm 0x20
806 #define DIO_PADDR __PORT8 0xFFFE39 /* DIO A Data Direction Register */
807 #define PADDR_PA0DDRm 0x01
808 #define PADDR_PA1DDRm 0x02
809 #define PADDR_PA2DDRm 0x04
810 #define PADDR_PA3DDRm 0x08
811 #define DIO_PBDDR __PORT8 0xFFFE3A /* DIO B Data Direction Register */
812 #define PBDDR_PB0DDRm 0x01
813 #define PBDDR_PB1DDRm 0x02
814 #define PBDDR_PB2DDRm 0x04
815 #define PBDDR_PB3DDRm 0x08
816 #define PBDDR_PB4DDRm 0x10
817 #define PBDDR_PB5DDRm 0x20
818 #define PBDDR_PB6DDRm 0x40
819 #define PBDDR_PB7DDRm 0x80
820 #define DIO_PCDDR __PORT8 0xFFFE3B /* DIO C Data Direction Register */
821 #define PCDDR_PC0DDRm 0x01
822 #define PCDDR_PC1DDRm 0x02
823 #define PCDDR_PC2DDRm 0x04
824 #define PCDDR_PC3DDRm 0x08
825 #define PCDDR_PC4DDRm 0x10
826 #define PCDDR_PC5DDRm 0x20
827 #define PCDDR_PC6DDRm 0x40
828 #define PCDDR_PC7DDRm 0x80
829 #define DIO_PDDDR __PORT8 0xFFFE3C /* DIO D Data Direction Register */
830 #define PDDDR_PD0DDRm 0x01
831 #define PDDDR_PD1DDRm 0x02
832 #define PDDDR_PD2DDRm 0x04
833 #define PDDDR_PD3DDRm 0x08
834 #define PDDDR_PD4DDRm 0x10
835 #define PDDDR_PD5DDRm 0x20
836 #define PDDDR_PD6DDRm 0x40
837 #define PDDDR_PD7DDRm 0x80
838 #define DIO_PEDDR __PORT8 0xFFFE3D /* DIO E Data Direction Register */
839 #define PEDDR_PE0DDRm 0x01
840 #define PEDDR_PE1DDRm 0x02
841 #define PEDDR_PE2DDRm 0x04
842 #define PEDDR_PE3DDRm 0x08
843 #define PEDDR_PE4DDRm 0x10
844 #define PEDDR_PE5DDRm 0x20
845 #define PEDDR_PE6DDRm 0x40
846 #define PEDDR_PE7DDRm 0x80
847 #define DIO_PFDDR __PORT8 0xFFFE3E /* DIO F Data Direction Register */
848 #define PFDDR_PF0DDRm 0x01
849 #define PFDDR_PF3DDRm 0x08
850 #define PFDDR_PF4DDRm 0x10
851 #define PFDDR_PF5DDRm 0x20
852 #define PFDDR_PF6DDRm 0x40
853 #define PFDDR_PF7DDRm 0x80
854 #define DIO_PAPCR __PORT8 0xFFFE40 /* DIO A MOS Pull-Up Control Register */
855 #define PAPCR_PA0PCRm 0x01
856 #define PAPCR_PA1PCRm 0x02
857 #define PAPCR_PA2PCRm 0x04
858 #define PAPCR_PA3PCRm 0x08
859 #define DIO_PBPCR __PORT8 0xFFFE41 /* DIO B MOS Pull-Up Control Register */
860 #define PBPCR_PB0PCRm 0x01
861 #define PBPCR_PB1PCRm 0x02
862 #define PBPCR_PB2PCRm 0x04
863 #define PBPCR_PB3PCRm 0x08
864 #define PBPCR_PB4PCRm 0x10
865 #define PBPCR_PB5PCRm 0x20
866 #define PBPCR_PB6PCRm 0x40
867 #define PBPCR_PB7PCRm 0x80
868 #define DIO_PCPCR __PORT8 0xFFFE42 /* DIO C MOS Pull-Up Control Register */
869 #define PCPCR_PC0PCRm 0x01
870 #define PCPCR_PC1PCRm 0x02
871 #define PCPCR_PC2PCRm 0x04
872 #define PCPCR_PC3PCRm 0x08
873 #define PCPCR_PC4PCRm 0x10
874 #define PCPCR_PC5PCRm 0x20
875 #define PCPCR_PC6PCRm 0x40
876 #define PCPCR_PC7PCRm 0x80
877 #define DIO_PDPCR __PORT8 0xFFFE43 /* DIO D MOS Pull-Up Control Register */
878 #define PDPCR_PD0PCRm 0x01
879 #define PDPCR_PD1PCRm 0x02
880 #define PDPCR_PD2PCRm 0x04
881 #define PDPCR_PD3PCRm 0x08
882 #define PDPCR_PD4PCRm 0x10
883 #define PDPCR_PD5PCRm 0x20
884 #define PDPCR_PD6PCRm 0x40
885 #define PDPCR_PD7PCRm 0x80
886 #define DIO_PEPCR __PORT8 0xFFFE44 /* DIO E MOS Pull-Up Control Register */
887 #define PEPCR_PE0PCRm 0x01
888 #define PEPCR_PE1PCRm 0x02
889 #define PEPCR_PE2PCRm 0x04
890 #define PEPCR_PE3PCRm 0x08
891 #define PEPCR_PE4PCRm 0x10
892 #define PEPCR_PE5PCRm 0x20
893 #define PEPCR_PE6PCRm 0x40
894 #define PEPCR_PE7PCRm 0x80
895 #define DIO_P3ODR __PORT8 0xFFFE46 /* DIO 3 Open Drain Control Register */
896 #define P3ODR_P30ODRm 0x01
897 #define P3ODR_P31ODRm 0x02
898 #define P3ODR_P32ODRm 0x04
899 #define P3ODR_P33ODRm 0x08
900 #define P3ODR_P34ODRm 0x10
901 #define P3ODR_P35ODRm 0x20
902 #define DIO_PAODR __PORT8 0xFFFE47 /* DIO A Open Drain Control Register */
903 #define PAODR_PA0ODRm 0x01
904 #define PAODR_PA1ODRm 0x02
905 #define PAODR_PA2ODRm 0x04
906 #define PAODR_PA3ODRm 0x08
907 #define DIO_PBODR __PORT8 0xFFFE48 /* DIO B Open Drain Control Register */
908 #define PBODR_PB0ODRm 0x01
909 #define PBODR_PB1ODRm 0x02
910 #define PBODR_PB2ODRm 0x04
911 #define PBODR_PB3ODRm 0x08
912 #define PBODR_PB4ODRm 0x10
913 #define PBODR_PB5ODRm 0x20
914 #define PBODR_PB6ODRm 0x40
915 #define PBODR_PB7ODRm 0x80
916 #define DIO_PCODR __PORT8 0xFFFE49 /* DIO C Open Drain Control Register */
917 #define PCODR_PC0ODRm 0x01
918 #define PCODR_PC1ODRm 0x02
919 #define PCODR_PC2ODRm 0x04
920 #define PCODR_PC3ODRm 0x08
921 #define PCODR_PC4ODRm 0x10
922 #define PCODR_PC5ODRm 0x20
923 #define PCODR_PC6ODRm 0x40
924 #define PCODR_PC7ODRm 0x80
925 /* Module Time pulse unit */
926 #define TPU_TCR3 __PORT8 0xFFFE80 /* Timer Control Register 3 */
927 #define TCR3_TPSC0m 0x01
928 #define TCR3_TPSC1m 0x02
929 #define TCR3_TPSC2m 0x04
930 #define TCR3_CKEG0m 0x08
931 #define TCR3_CKEG1m 0x10
932 #define TCR3_CCLR0m 0x20
933 #define TCR3_CCLR1m 0x40
934 #define TCR3_CCLR2m 0x80
935 #define TPU_TMDR3 __PORT8 0xFFFE81 /* Timer Mode Register 3 */
936 #define TMDR3_MD0m 0x01
937 #define TMDR3_MD1m 0x02
938 #define TMDR3_MD2m 0x04
939 #define TMDR3_MD3m 0x08
940 #define TMDR3_BFAm 0x10
941 #define TMDR3_BFBm 0x20
942 #define TPU_TIOR3H __PORT8 0xFFFE82 /* Timer IO Control Register 3H */
943 #define TIOR3H_IOA0m 0x01
944 #define TIOR3H_IOA1m 0x02
945 #define TIOR3H_IOA2m 0x04
946 #define TIOR3H_IOA3m 0x08
947 #define TIOR3H_IOB0m 0x10
948 #define TIOR3H_IOB1m 0x20
949 #define TIOR3H_IOB2m 0x40
950 #define TIOR3H_IOB3m 0x80
951 #define TPU_TIOR3L __PORT8 0xFFFE83 /* Timer IO Control Register 3L */
952 #define TIOR3L_IOC0m 0x01
953 #define TIOR3L_IOC1m 0x02
954 #define TIOR3L_IOC2m 0x04
955 #define TIOR3L_IOC3m 0x08
956 #define TIOR3L_IOD0m 0x10
957 #define TIOR3L_IOD1m 0x20
958 #define TIOR3L_IOD2m 0x40
959 #define TIOR3L_IOD3m 0x80
960 #define TPU_TIER3 __PORT8 0xFFFE84 /* -Timer INT Enable Register 3 */
961 #define TIER3_TGIEAm 0x01
962 #define TIER3_TGIEBm 0x02
963 #define TIER3_TGIECm 0x04
964 #define TIER3_TGIEDm 0x08
965 #define TIER3_TCIEVm 0x10
966 #define TIER3_TTGEm 0x80
967 #define TPU_TSR3 __PORT8 0xFFFE85 /* Timer Status Register 3 */
968 #define TSR3_TGFAm 0x01
969 #define TSR3_TGFBm 0x02
970 #define TSR3_TGFCm 0x04
971 #define TSR3_TGFDm 0x08
972 #define TSR3_TCFVm 0x10
973 #define TPU_TCNT3 __PORT16 0xFFFE86 /* Timer Counter 3 */
974 #define TPU_TGR3A __PORT16 0xFFFE88 /* Timer General Register 3A */
975 #define TPU_TGR3B __PORT16 0xFFFE8A /* Timer General Register 3B */
976 #define TPU_TGR3C __PORT16 0xFFFE8C /* Timer General Register 3C */
977 #define TPU_TGR3D __PORT16 0xFFFE8E /* Timer General Register 3D */
978 #define TPU_TCR4 __PORT8 0xFFFE90 /* Timer Control Register 4 */
979 #define TCR4_TPSC0m 0x01
980 #define TCR4_TPSC1m 0x02
981 #define TCR4_TPSC2m 0x04
982 #define TCR4_CKEG0m 0x08
983 #define TCR4_CKEG1m 0x10
984 #define TCR4_CCLR0m 0x20
985 #define TCR4_CCLR1m 0x40
986 #define TPU_TMDR4 __PORT8 0xFFFE91 /* Timer Mode Register 4 */
987 #define TMDR4_MD0m 0x01
988 #define TMDR4_MD1m 0x02
989 #define TMDR4_MD2m 0x04
990 #define TMDR4_MD3m 0x08
991 #define TPU_TIOR4 __PORT8 0xFFFE92 /* Timer IO Control Register 4 */
992 #define TIOR4_IOA0m 0x01
993 #define TIOR4_IOA1m 0x02
994 #define TIOR4_IOA2m 0x04
995 #define TIOR4_IOA3m 0x08
996 #define TIOR4_IOB0m 0x10
997 #define TIOR4_IOB1m 0x20
998 #define TIOR4_IOB2m 0x40
999 #define TIOR4_IOB3m 0x80
1000 #define TPU_TIER4 __PORT8 0xFFFE94 /* Timer INT Enable Register 4 */
1001 #define TIER4_TGIEAm 0x01
1002 #define TIER4_TGIEBm 0x02
1003 #define TIER4_TCIEVm 0x10
1004 #define TIER4_TCIEUm 0x20
1005 #define TIER4_TTGEm 0x80
1006 #define TPU_TSR4 __PORT8 0xFFFE95 /* Timer Status Register 4 */
1007 #define TSR4_TGFAm 0x01
1008 #define TSR4_TGFBm 0x02
1009 #define TSR4_TCFVm 0x10
1010 #define TSR4_TCFUm 0x20
1011 #define TSR4_TCFDm 0x80
1012 #define TPU_TCNT4 __PORT16 0xFFFE96 /* Timer Counter 4 */
1013 #define TPU_TGR4A __PORT16 0xFFFE98 /* Timer General Register 4A */
1014 #define TPU_TGR4B __PORT16 0xFFFE9A /* Timer General Register 4B */
1015 #define TPU_TCR5 __PORT8 0xFFFEA0 /* Timer Control Register 5 */
1016 #define TCR5_TPSC0m 0x01
1017 #define TCR5_TPSC1m 0x02
1018 #define TCR5_TPSC2m 0x04
1019 #define TCR5_CKEG0m 0x08
1020 #define TCR5_CKEG1m 0x10
1021 #define TCR5_CCLR0m 0x20
1022 #define TCR5_CCLR1m 0x40
1023 #define TPU_TMDR5 __PORT8 0xFFFEA1 /* Timer Mode Register 5 */
1025 #define TPU_TIOR5 __PORT8 0xFFFEA2 /* Timer IO Control Register 5 */
1026 #define TIOR5_IOA0m 0x01
1027 #define TIOR5_IOA1m 0x02
1028 #define TIOR5_IOA2m 0x04
1029 #define TIOR5_IOA3m 0x08
1030 #define TIOR5_IOB0m 0x10
1031 #define TIOR5_IOB1m 0x20
1032 #define TIOR5_IOB2m 0x40
1033 #define TIOR5_IOB3m 0x80
1034 #define TPU_TIER5 __PORT8 0xFFFEA4 /* Timer INT Enable Register 5 */
1035 #define TIER5_TGIEAm 0x01
1036 #define TIER5_TGIEBm 0x02
1037 #define TIER5_TCIEVm 0x10
1038 #define TIER5_TCIEUm 0x20
1039 #define TIER5_TTGEm 0x80
1040 #define TPU_TSR5 __PORT8 0xFFFEA5 /* Timer Status Register 5 */
1041 #define TSR5_TGFAm 0x01
1042 #define TSR5_TGFBm 0x02
1043 #define TSR5_TCFVm 0x10
1044 #define TSR5_TCFUm 0x20
1045 #define TSR5_TCFDm 0x80
1046 #define TPU_TCNT5 __PORT16 0xFFFEA6 /* Timer Counter 5 */
1047 #define TPU_TGR5A __PORT16 0xFFFEA8 /* Timer General Register 5A */
1048 #define TPU_TGR5B __PORT16 0xFFFEAA /* Timer General Register 5B */
1049 #define TPU_TSTR __PORT8 0xFFFEB0 /* Timer Start Register */
1050 #define TSTR_CST0m 0x01
1051 #define TSTR_CST1m 0x02
1052 #define TSTR_CST2m 0x04
1053 #define TSTR_CST3m 0x08
1054 #define TSTR_CST4m 0x10
1055 #define TSTR_CST5m 0x20
1056 #define TPU_TSYR __PORT8 0xFFFEB1 /* Timer Synchro Register */
1057 #define TSYR_SYNC0m 0x01
1058 #define TSYR_SYNC1m 0x02
1059 #define TSYR_SYNC2m 0x04
1060 #define TSYR_SYNC3m 0x08
1061 #define TSYR_SYNC4m 0x10
1062 #define TSYR_SYNC5m 0x20
1063 /* Module Interrupt */
1064 #define INT_IPRA __PORT8 0xFFFEC0 /* Interrupt Priority Register A */
1065 #define IPRA_IPR0m 0x01
1066 #define IPRA_IPR1m 0x02
1067 #define IPRA_IPR2m 0x04
1068 #define IPRA_IPR4m 0x10
1069 #define IPRA_IPR5m 0x20
1070 #define IPRA_IPR6m 0x40
1071 #define INT_IPRB __PORT8 0xFFFEC1 /* Interrupt Priority Register B */
1072 #define IPRB_IPR0m 0x01
1073 #define IPRB_IPR1m 0x02
1074 #define IPRB_IPR2m 0x04
1075 #define IPRB_IPR4m 0x10
1076 #define IPRB_IPR5m 0x20
1077 #define IPRB_IPR6m 0x40
1078 #define INT_IPRC __PORT8 0xFFFEC2 /* Interrupt Priority Register C */
1079 #define IPRC_IPR0m 0x01
1080 #define IPRC_IPR1m 0x02
1081 #define IPRC_IPR2m 0x04
1082 #define INT_IPRD __PORT8 0xFFFEC3 /* Interrupt Priority Register D */
1083 #define IPRD_IPR4m 0x10
1084 #define IPRD_IPR5m 0x20
1085 #define IPRD_IPR6m 0x40
1086 #define INT_IPRE __PORT8 0xFFFEC4 /* Interrupt Priority Register E */
1087 #define IPRE_IPR0m 0x01
1088 #define IPRE_IPR1m 0x02
1089 #define IPRE_IPR2m 0x04
1090 #define IPRE_IPR4m 0x10
1091 #define IPRE_IPR5m 0x20
1092 #define IPRE_IPR6m 0x40
1093 #define INT_IPRF __PORT8 0xFFFEC5 /* Interrupt Priority Register F */
1094 #define IPRF_IPR0m 0x01
1095 #define IPRF_IPR1m 0x02
1096 #define IPRF_IPR2m 0x04
1097 #define IPRF_IPR4m 0x10
1098 #define IPRF_IPR5m 0x20
1099 #define IPRF_IPR6m 0x40
1100 #define INT_IPRG __PORT8 0xFFFEC6 /* Interrupt Priority Register G */
1101 #define IPRG_IPR0m 0x01
1102 #define IPRG_IPR1m 0x02
1103 #define IPRG_IPR2m 0x04
1104 #define IPRG_IPR4m 0x10
1105 #define IPRG_IPR5m 0x20
1106 #define IPRG_IPR6m 0x40
1107 #define INT_IPRH __PORT8 0xFFFEC7 /* Interrupt Priority Register H */
1108 #define IPRH_IPR0m 0x01
1109 #define IPRH_IPR1m 0x02
1110 #define IPRH_IPR2m 0x04
1111 #define IPRH_IPR4m 0x10
1112 #define IPRH_IPR5m 0x20
1113 #define IPRH_IPR6m 0x40
1114 #define INT_IPRJ __PORT8 0xFFFEC9 /* Interrupt Priority Register J */
1115 #define IPRJ_IPR0m 0x01
1116 #define IPRJ_IPR1m 0x02
1117 #define IPRJ_IPR2m 0x04
1118 #define INT_IPRK __PORT8 0xFFFECA /* Interrupt Priority Register K */
1119 #define IPRK_IPR0m 0x01
1120 #define IPRK_IPR1m 0x02
1121 #define IPRK_IPR2m 0x04
1122 #define IPRK_IPR4m 0x10
1123 #define IPRK_IPR5m 0x20
1124 #define IPRK_IPR6m 0x40
1125 #define INT_IPRM __PORT8 0xFFFECC /* Interrupt Priority Register M */
1126 #define IPRM_IPR0m 0x01
1127 #define IPRM_IPR1m 0x02
1128 #define IPRM_IPR2m 0x04
1129 #define IPRM_IPR4m 0x10
1130 #define IPRM_IPR5m 0x20
1131 #define IPRM_IPR6m 0x40
1132 /* Module BUS controler */
1133 #define BUS_ABWCR __PORT8 0xFFFED0 /* Bus Width Control Register */
1134 #define ABWCR_ABW0m 0x01
1135 #define ABWCR_ABW1m 0x02
1136 #define ABWCR_ABW2m 0x04
1137 #define ABWCR_ABW3m 0x08
1138 #define ABWCR_ABW4m 0x10
1139 #define ABWCR_ABW5m 0x20
1140 #define ABWCR_ABW6m 0x40
1141 #define ABWCR_ABW7m 0x80
1142 #define BUS_ASTCR __PORT8 0xFFFED1 /* Access State Control Register */
1143 #define ASTCR_AST0m 0x01
1144 #define ASTCR_AST1m 0x02
1145 #define ASTCR_AST2m 0x04
1146 #define ASTCR_AST3m 0x08
1147 #define ASTCR_AST4m 0x10
1148 #define ASTCR_AST5m 0x20
1149 #define ASTCR_AST6m 0x40
1150 #define ASTCR_AST7m 0x80
1151 #define BUS_WCRH __PORT8 0xFFFED2 /* Wait Control Register H */
1152 #define WCRH_W40m 0x01
1153 #define WCRH_W41m 0x02
1154 #define WCRH_W50m 0x04
1155 #define WCRH_W51m 0x08
1156 #define WCRH_W60m 0x10
1157 #define WCRH_W61m 0x20
1158 #define WCRH_W70m 0x40
1159 #define WCRH_W71m 0x80
1160 #define BUS_WCRL __PORT8 0xFFFED3 /* Wait Control Register L */
1161 #define WCRL_W00m 0x01
1162 #define WCRL_W01m 0x02
1163 #define WCRL_W10m 0x04
1164 #define WCRL_W11m 0x08
1165 #define WCRL_W20m 0x10
1166 #define WCRL_W21m 0x20
1167 #define WCRL_W30m 0x40
1168 #define WCRL_W31m 0x80
1169 #define BUS_BCRH __PORT8 0xFFFED4 /* Bus Control Register H */
1170 #define BCRH_BRSTS0m 0x08
1171 #define BCRH_BRSTS1m 0x10
1172 #define BCRH_BRSTRMm 0x20
1173 #define BCRH_ICIS0m 0x40
1174 #define BCRH_ICIS1m 0x80
1175 #define BUS_BCRL __PORT8 0xFFFED5 /* Bus Control Register L */
1176 #define BCRL_WDBEm 0x02
1178 #define FLM_RAMER __PORT8 0xFFFEDB /* RAM Emulation Register */
1179 #define RAMER_RAM0m 0x01
1180 #define RAMER_RAM1m 0x02
1181 #define RAMER_RAM2m 0x04
1182 #define RAMER_RAMxm 0x07
1183 #define RAMER_RAMSm 0x08
1186 #define DIO_P1DR __PORT8 0xFFFF00 /* DIO 1 Data Register */
1187 #define P1DR_P10DRm 0x01
1188 #define P1DR_P11DRm 0x02
1189 #define P1DR_P12DRm 0x04
1190 #define P1DR_P13DRm 0x08
1191 #define P1DR_P14DRm 0x10
1192 #define P1DR_P15DRm 0x20
1193 #define P1DR_P16DRm 0x40
1194 #define P1DR_P17DRm 0x80
1195 #define DIO_P3DR __PORT8 0xFFFF02 /* DIO 3 Data Register */
1196 #define P3DR_P30DRm 0x01
1197 #define P3DR_P31DRm 0x02
1198 #define P3DR_P32DRm 0x04
1199 #define P3DR_P33DRm 0x08
1200 #define P3DR_P34DRm 0x10
1201 #define P3DR_P35DRm 0x20
1202 #define DIO_PADR __PORT8 0xFFFF09 /* DIO A Data Register */
1203 #define PADR_PA0DRm 0x01
1204 #define PADR_PA1DRm 0x02
1205 #define PADR_PA2DRm 0x04
1206 #define PADR_PA3DRm 0x08
1207 #define DIO_PBDR __PORT8 0xFFFF0A /* DIO B Data Register */
1208 #define PBDR_PB0DRm 0x01
1209 #define PBDR_PB1DRm 0x02
1210 #define PBDR_PB2DRm 0x04
1211 #define PBDR_PB3DRm 0x08
1212 #define PBDR_PB4DRm 0x10
1213 #define PBDR_PB5DRm 0x20
1214 #define PBDR_PB6DRm 0x40
1215 #define PBDR_PB7DRm 0x80
1216 #define DIO_PCDR __PORT8 0xFFFF0B /* DIO C Data Register */
1217 #define PCDR_PC0DRm 0x01
1218 #define PCDR_PC1DRm 0x02
1219 #define PCDR_PC2DRm 0x04
1220 #define PCDR_PC3DRm 0x08
1221 #define PCDR_PC4DRm 0x10
1222 #define PCDR_PC5DRm 0x20
1223 #define PCDR_PC6DRm 0x40
1224 #define PCDR_PC7DRm 0x80
1225 #define DIO_PDDR __PORT8 0xFFFF0C /* DIO D Data Register */
1226 #define PDDR_PD0DRm 0x01
1227 #define PDDR_PD1DRm 0x02
1228 #define PDDR_PD2DRm 0x04
1229 #define PDDR_PD3DRm 0x08
1230 #define PDDR_PD4DRm 0x10
1231 #define PDDR_PD5DRm 0x20
1232 #define PDDR_PD6DRm 0x40
1233 #define PDDR_PD7DRm 0x80
1234 #define DIO_PEDR __PORT8 0xFFFF0D /* DIO E Data Register */
1235 #define PEDR_PE0DRm 0x01
1236 #define PEDR_PE1DRm 0x02
1237 #define PEDR_PE2DRm 0x04
1238 #define PEDR_PE3DRm 0x08
1239 #define PEDR_PE4DRm 0x10
1240 #define PEDR_PE5DRm 0x20
1241 #define PEDR_PE6DRm 0x40
1242 #define PEDR_PE7DRm 0x80
1243 #define DIO_PFDR __PORT8 0xFFFF0E /* DIO F Data Register */
1244 #define PFDR_PF0DRm 0x01
1245 #define PFDR_PF1DRm 0x02
1246 #define PFDR_PF2DRm 0x04
1247 #define PFDR_PF3DRm 0x08
1248 #define PFDR_PF4DRm 0x10
1249 #define PFDR_PF5DRm 0x20
1250 #define PFDR_PF6DRm 0x40
1251 #define PFDR_PF7DRm 0x80
1253 /* Module Time pulse unit */ //see other definitions at the end of the file
1254 #define TPU_TCR0 __PORT8 0xFFFF10 /* Timer Control Register 0 */
1255 #define TCR0_TPSC0m 0x01
1256 #define TCR0_TPSC1m 0x02
1257 #define TCR0_TPSC2m 0x04
1258 #define TCR0_CKEG0m 0x08
1259 #define TCR0_CKEG1m 0x10
1260 #define TCR0_CCLR0m 0x20
1261 #define TCR0_CCLR1m 0x40
1262 #define TCR0_CCLR2m 0x80
1263 #define TPU_TMDR0 __PORT8 0xFFFF11 /* Timer Mode Register 0 */
1264 #define TMDR0_MD0m 0x01
1265 #define TMDR0_MD1m 0x02
1266 #define TMDR0_MD2m 0x04
1267 #define TMDR0_MD3m 0x08
1268 #define TMDR0_BFAm 0x10
1269 #define TMDR0_BFBm 0x20
1270 #define TPU_TIOR0H __PORT8 0xFFFF12 /* Timer IO Control Register 0H */
1271 #define TIOR0H_IOA0m 0x01
1272 #define TIOR0H_IOA1m 0x02
1273 #define TIOR0H_IOA2m 0x04
1274 #define TIOR0H_IOA3m 0x08
1275 #define TIOR0H_IOB0m 0x10
1276 #define TIOR0H_IOB1m 0x20
1277 #define TIOR0H_IOB2m 0x40
1278 #define TIOR0H_IOB3m 0x80
1279 #define TPU_TIOR0L __PORT8 0xFFFF13 /* Timer IO Control Register 0L */
1280 #define TIOR0L_IOC0m 0x01
1281 #define TIOR0L_IOC1m 0x02
1282 #define TIOR0L_IOC2m 0x04
1283 #define TIOR0L_IOC3m 0x08
1284 #define TIOR0L_IOD0m 0x10
1285 #define TIOR0L_IOD1m 0x20
1286 #define TIOR0L_IOD2m 0x40
1287 #define TIOR0L_IOD3m 0x80
1288 #define TPU_TIER0 __PORT8 0xFFFF14 /* Timer INT Enable Register 0 */
1289 #define TIER0_TGIEAm 0x01
1290 #define TIER0_TGIEBm 0x02
1291 #define TIER0_TGIECm 0x04
1292 #define TIER0_TGIEDm 0x08
1293 #define TIER0_TCIEVm 0x10
1294 #define TIER0_TTGEm 0x80
1295 #define TPU_TSR0 __PORT8 0xFFFF15 /* Timer Status Register 0 */
1296 #define TSR0_TGFAm 0x01
1297 #define TSR0_TGFBm 0x02
1298 #define TSR0_TGFCm 0x04
1299 #define TSR0_TGFDm 0x08
1300 #define TSR0_TCFVm 0x10
1301 #define TPU_TCNT0 __PORT16 0xFFFF16 /* Timer Counter 0 */
1302 #define TPU_TGR0A __PORT16 0xFFFF18 /* Timer General Register 0A */
1303 #define TPU_TGR0B __PORT16 0xFFFF1A /* Timer General Register 0B */
1304 #define by_standbym 0x02
1305 #define data_tom 0x02
1306 #define data_tom 0x02
1307 #define to_slavem 0x02
1308 #define TPU_TGR0C __PORT16 0xFFFF1C /* Timer General Register 0C */
1309 #define TPU_TGR0D __PORT16 0xFFFF1E /* Timer General Register 0D */
1310 #define TPU_TCR1 __PORT8 0xFFFF20 /* Timer Control Register 1 */
1311 #define TCR1_TPSC0m 0x01
1312 #define TCR1_TPSC1m 0x02
1313 #define TCR1_TPSC2m 0x04
1314 #define TCR1_CKEG0m 0x08
1315 #define TCR1_CKEG1m 0x10
1316 #define TCR1_CCLR0m 0x20
1317 #define TCR1_CCLR1m 0x40
1318 #define TPU_TMDR1 __PORT8 0xFFFF21 /* Timer Mode Register 1 */
1319 #define TMDR1_MD0m 0x01
1320 #define TMDR1_MD1m 0x02
1321 #define TMDR1_MD2m 0x04
1322 #define TMDR1_MD3m 0x08
1323 #define TPU_TIOR1 __PORT8 0xFFFF22 /* Timer IO Control Register 1 */
1324 #define TIOR1_IOA0m 0x01
1325 #define TIOR1_IOA1m 0x02
1326 #define TIOR1_IOA2m 0x04
1327 #define TIOR1_IOA3m 0x08
1328 #define TIOR1_IOB0m 0x10
1329 #define TIOR1_IOB1m 0x20
1330 #define TIOR1_IOB2m 0x40
1331 #define TIOR1_IOB3m 0x80
1332 #define TPU_TIER1 __PORT8 0xFFFF24 /* Timer INT Enable Register 1 */
1333 #define TIER1_TGIEAm 0x01
1334 #define TIER1_TGIEBm 0x02
1335 #define TIER1_TCIEVm 0x10
1336 #define TIER1_TCIEUm 0x20
1337 #define TIER1_TTGEm 0x80
1338 #define TPU_TSR1 __PORT8 0xFFFF25 /* Timer Status Register 1 */
1339 #define TSR1_TGFAm 0x01
1340 #define TSR1_TGFBm 0x02
1341 #define TSR1_TCFVm 0x10
1342 #define TSR1_TCFUm 0x20
1343 #define TSR1_TCFDm 0x80
1344 #define TPU_TCNT1 __PORT16 0xFFFF26 /* Timer Counter 1 */
1345 #define TPU_TGR1A __PORT16 0xFFFF28 /* Timer General Register 1A */
1346 #define TPU_TGR1B __PORT16 0xFFFF2A /* Timer General Register 1B */
1347 #define TPU_TCR2 __PORT8 0xFFFF30 /* Timer Control Register 2 */
1348 #define TCR2_TPSC0m 0x01
1349 #define TCR2_TPSC1m 0x02
1350 #define TCR2_TPSC2m 0x04
1351 #define TCR2_CKEG0m 0x08
1352 #define TCR2_CKEG1m 0x10
1353 #define TCR2_CCLR0m 0x20
1354 #define TCR2_CCLR1m 0x40
1355 #define TPU_TMDR2 __PORT8 0xFFFF31 /* Timer Mode Register 2 */
1356 #define TMDR2_MD0m 0x01
1357 #define TMDR2_MD1m 0x02
1358 #define TMDR2_MD2m 0x04
1359 #define TMDR2_MD3m 0x08
1360 #define TPU_TIOR2 __PORT8 0xFFFF32 /* Timer IO Control Register 2 */
1361 #define TIOR2_IOA0m 0x01
1362 #define TIOR2_IOA1m 0x02
1363 #define TIOR2_IOA2m 0x04
1364 #define TIOR2_IOA3m 0x08
1365 #define TIOR2_IOB0m 0x10
1366 #define TIOR2_IOB1m 0x20
1367 #define TIOR2_IOB2m 0x40
1368 #define TIOR2_IOB3m 0x80
1369 #define TPU_TIER2 __PORT8 0xFFFF34 /* Timer INT Enable Register 2 */
1370 #define TIER2_TGIEAm 0x01
1371 #define TIER2_TGIEBm 0x02
1372 #define TIER2_TCIEVm 0x10
1373 #define TIER2_TCIEUm 0x20
1374 #define TIER2_TTGEm 0x80
1375 #define TPU_TSR2 __PORT8 0xFFFF35 /* Timer Status Register 2 */
1376 #define TSR2_TGFAm 0x01
1377 #define TSR2_TGFBm 0x02
1378 #define TSR2_TCFVm 0x10
1379 #define TSR2_TCFUm 0x20
1380 #define TSR2_TCFDm 0x80
1381 #define TPU_TCNT2 __PORT16 0xFFFF36 /* Timer Counter 2 */
1382 #define TPU_TGR2A __PORT16 0xFFFF38 /* Timer General Register 2A */
1383 #define TPU_TGR2B __PORT16 0xFFFF3A /* Timer General Register 2B */
1385 /* Module Watchdog timer */
1386 /* WDT0 register definitions start */
1387 #define WDT_WTCSR0r __PORT8 0xFFFF74 /* Timer ControlStatus Register 0 (RD/WC7) */
1388 #define WDT_WTCSR0w __PORT16 0xFFFF74 /* writte address - password 0xa500 */
1389 #define WTCSR0_CKS0m 0x01
1390 #define WTCSR0_CKS1m 0x02
1391 #define WTCSR0_CKS2m 0x04
1392 #define WTCSR0_CKSxm 0x07
1393 #define WTCSR0_TMEm 0x20
1394 #define WTCSR0_WTITm 0x40
1395 #define WTCSR0_WOVFm 0x80
1396 #define WDT_WTCNT0r __PORT8 0xFFFF75 /* Timer Counter 0 (RD) */
1397 #define WDT_WTCNT0w __PORT16 0xFFFF74 /* writte address - password 0x5a00 */
1398 #define WDT_WRSTCSRr __PORT8 0xFFFF77 /* Reset ControlStatus Register (RD/WC7) */
1399 #define WDT_WRSTCSRw __PORT16 0xFFFF76 /* clear WOVF - password 0xa500 */
1400 /* set bits - password 0x5a00 */
1401 #define WRSTCSR_RSTSm 0x20
1402 #define WRSTCSR_RSTEm 0x40
1403 #define WRSTCSR_WOVFm 0x80
1404 /* WDT0 register definitions end */
1406 /* SCI common registers and bits start */
1408 /* Receive Data Register (RDR) */
1409 /* Transmit Data Register (TDR) */
1410 /* Serial Mode Register (SMR) */
1411 #define SMR_CKS0m 0x01
1412 #define SMR_CKS1m 0x02
1413 #define SMR_CKSxm 0x03 /* Clock 3=/64, 2=/16, 1=/4, 0=/1 */
1414 #define SMR_MPm 0x04 /* 1=Multiprocessor format selected */
1415 #define SMR_STOPm 0x08 /* 1=2 stop bits, 0=1 stop bit */
1416 #define SMR_OEm 0x10 /* 1=Odd parity, 0=Even */
1417 #define SMR_PEm 0x20 /* 1=Parity addition and checking enabled */
1418 #define SMR_CHRm 0x40 /* 1=7-bit data, 0=8-bit */
1419 #define SMR_CAm 0x80 /* 1=Clocked, 0=Asynchronous */
1420 #define SCI_SMR_8N1 (0|0|0)
1421 #define SCI_SMR_7N1 (SMR_CHRm|0|0)
1422 #define SCI_SMR_8N2 (0 |0|SMR_STOPm)
1423 #define SCI_SMR_7N2 (SMR_CHRm|0|SMR_STOPm)
1424 #define SCI_SMR_8E1 (0 |SMR_PEm|0)
1425 #define SCI_SMR_7E1 (SMR_CHRm|SMR_PEm|0)
1426 #define SCI_SMR_8O1 (0 |SMR_PEm|SMR_OEm)
1427 #define SCI_SMR_7O1 (SMR_CHRm|SMR_PEm|SMR_OEm)
1428 /* Serial Control Register (SCR) */
1429 #define SCR_CKE0m 0x01 /* Clock Enable */
1430 #define SCR_CKE1m 0x02 /* */
1431 #define SCR_TEIEm 0x04 /* Transmit end interrupt (TEI) */
1432 #define SCR_MPIEm 0x08 /* Only multiprocessor RXI interrupt enabled */
1433 #define SCR_REm 0x10 /* Reception enabled */
1434 #define SCR_TEm 0x20 /* Transmission enabled* */
1435 #define SCR_RIEm 0x40 /* RXI interrupt requests enabled */
1436 #define SCR_TIEm 0x80 /* TXI interrupt requests enabled */
1437 /* Serial Status Register (SSR) */
1438 #define SSR_MPBTm 0x01 /* Value to send as bit 8 */
1439 #define SSR_MPBm 0x02 /* MP Bit 8 received value */
1440 #define SSR_TENDm 0x04 /* Transmit End */
1441 #define SSR_PERm 0x08 /* Parity error */
1442 #define SSR_FERm 0x10 /* Framing error */
1443 #define SSR_ORERm 0x20 /* Receive overflow */
1444 #define SSR_RDRFm 0x40 /* Set when reception ends normally */
1445 #define SSR_TDREm 0x80 /* Set when TDR empty or SCR_TE=0 */
1446 /* Bit Rate Register (BRR) */
1447 /* for async set to N=Fsys/(32*2^(2n)*baud)-1 where n=SMR_CKS */
1448 /* for sync set to N=Fsys/(4*2^(2n)*baud)-1 */
1449 /* Smart Card Mode Register (SCMR) */
1450 #define SCMR_SMIFm 0x01 /* 1=Smart card interface enabled */
1451 #define SCMR_SINVm 0x04 /* 1=TDR contents inverted */
1452 #define SCMR_SDIRm 0x08 /* 1=MSB-first, 0=LSB-first */
1453 /* I2C Bus Mode / Slave Address Register (ICMR/SAR)*/
1454 /* only for SCI0 and SCI1 */
1455 #define ICMR_BC0m 0x01 /* Bit Counter */
1456 #define ICMR_BC1m 0x02
1457 #define ICMR_BC2m 0x04
1458 #define ICMR_BCm (ICMR_BC0m|ICMR_BC1m|ICMR_BC2m)
1459 #define ICMR_CKS0m 0x08 /* Serial Clock Select */
1460 #define ICMR_CKS1m 0x10
1461 #define ICMR_CKS2m 0x20
1462 #define ICMR_CKSm (ICMR_CKS0m|ICMR_CKS1m|ICMR_CKS2m)
1463 #define ICMR_WAITm 0x40 /* 1 .. Wait between data and acknowledge */
1464 #define ICMR_MLSm 0x80 /* 0 .. MSB-first / 1 .. LSB-first */
1465 /* I2C Bus Control Register (ICCR) */
1466 #define ICCR_SCPm 0x01 /* Write 0 with BBSY to start/stop */
1467 #define ICCR_IRICm 0x02 /* 1 => interrupt requested */
1468 #define ICCR_BBSYm 0x04 /* 1 => bus is busy */
1469 #define ICCR_ACKEm 0x08 /* 1 => stop when no ACK detected */
1470 #define ICCR_TRSm 0x10 /* 1 .. transmit / 0 .. receive */
1471 #define ICCR_MSTm 0x20 /* 1 .. master mode / 0 .. slave mode */
1472 #define ICCR_IEICm 0x40 /* Interrupts enabled */
1473 #define ICCR_ICEm 0x80 /* 1 .. IIC enabled (ICMR,ICDR accessible) */
1474 /* 0 .. IIC disabled (SAR,SARX accessible) */
1475 /* IIC Bus Status Register (ICSR) */
1476 #define ICSR_ACKBm 0x01 /* Acknowledge Bit */
1477 #define ICSR_ADZm 0x02 /* General Call Address Recognition */
1478 #define ICSR_AASm 0x04 /* Slave Address Recognition */
1479 #define ICSR_ALm 0x08 /* Arbitration Lost */
1480 #define ICSR_AASXm 0x10 /* Second Slave Address Recognition */
1481 #define ICSR_IRTRm 0x20 /* Continuous Transmission/Reception Interrupt */
1482 #define ICSR_STOPm 0x40 /* Normal Stop Condition Detection Flag */
1483 #define ICSR_ESTPm 0x80 /* Error Stop Condition Detection Flag */
1485 /* SCI common registers and bits end */
1488 #define SCI_SMR0 __PORT8 0xFFFF78 /* Serial Mode Register 0 */
1489 #define SMR0_CKS0m 0x01
1490 #define SMR0_CKS1m 0x02
1491 #define SMR0_MPm 0x04
1492 #define SMR0_STOPm 0x08
1493 #define SMR0_OEm 0x10
1494 #define SMR0_PEm 0x20
1495 #define SMR0_CHRm 0x40
1496 #define SMR0_CAm 0x80
1497 #define Smart_SMR0 __PORT8 0xFFFF78 /* Smart Card Mode Register 0 */
1498 #define IIC_ICCR0 __PORT8 0xFFFF78 /* I2C Bus Control Register */
1499 #define SCI_BRR0 __PORT8 0xFFFF79 /* Bit Rate Register 0 */
1500 #define Smart_BRR0 __PORT8 0xFFFF79 /* Bit Rate Register 0 */
1501 #define IIC_ICSR0 __PORT8 0xFFFF79 /* I2C Bus Status Register */
1502 #define SCI_SCR0 __PORT8 0xFFFF7A /* Serial Control Register 0 */
1503 #define Smart_SCR0 __PORT8 0xFFFF7A /* Serial Control Register 0 */
1504 #define SCR0_CKE0m 0x01
1505 #define SCR0_CKE1m 0x02
1506 #define SCR0_TEIEm 0x04
1507 #define SCR0_MPIEm 0x08
1508 #define SCR0_REm 0x10
1509 #define SCR0_TEm 0x20
1510 #define SCR0_RIEm 0x40
1511 #define SCR0_TIEm 0x80
1512 #define SCI_TDR0 __PORT8 0xFFFF7B /* Transmit Data Register 0 */
1513 #define Smart_TDR0 __PORT8 0xFFFF7B /* Transmit Data Register 0 */
1514 #define SCI_SSR0 __PORT8 0xFFFF7C /* Serial Status Register 0 */
1515 #define SSR0_MPBTm 0x01
1516 #define SSR0_MPBm 0x02
1517 #define SSR0_TENDm 0x04
1518 #define SSR0_PERm 0x08
1519 #define SSR0_FERm 0x10
1520 #define SSR0_ORERm 0x20
1521 #define SSR0_RDRFm 0x40
1522 #define SSR0_TDREm 0x80
1523 #define Smart_SSR0 __PORT8 0xFFFF7C /* Serial Status Register 0 */
1524 #define SCI_RDR0 __PORT8 0xFFFF7D /* Receive Data Register 0 */
1525 #define SCI_SCMR0 __PORT8 0xFFFF7E /* Smart Card Mode Register 0 */
1526 #define SCMR0_SMIFm 0x01
1527 #define SCMR0_SINVm 0x04
1528 #define SCMR0_SDIRm 0x08
1529 #define Smart_SCMR0 __PORT8 0xFFFF7E /* Smart Card Mode Register 0 */
1530 #define IIC_ICDR0 __PORT8 0xFFFF7E /* I2C Bus Data Register */
1531 #define IIC_SARX0 __PORT8 0xFFFF7E /* 2nd Slave Address Register */
1532 #define IIC_ICMR0 __PORT8 0xFFFF7F /* I2C Bus Mode Register */
1533 #define ICMR0_BC0FSm 0x01
1534 #define ICMR0_BC1m 0x02
1535 #define ICMR0_BC2m 0x04
1536 #define ICMR0_CKS0m 0x08
1537 #define ICMR0_CKS1m 0x10
1538 #define ICMR0_CKS2m 0x20
1539 #define ICMR0_WAITm 0x40
1540 #define ICMR0_MLSm 0x80
1541 #define IIC_SAR0 __PORT8 0xFFFF7F /* Slave Address Register */
1542 #define SCI_SMR1 __PORT8 0xFFFF80 /* Serial Mode Register 1 */
1543 #define SMR1_CKS0m 0x01
1544 #define SMR1_CKS1m 0x02
1545 #define SMR1_MPm 0x04
1546 #define SMR1_STOPm 0x08
1547 #define SMR1_OEm 0x10
1548 #define SMR1_PEm 0x20
1549 #define SMR1_CHRm 0x40
1550 #define SMR1_CAm 0x80
1551 #define IIC_ICCR1 __PORT8 0xFFFF80 /* I2C Bus Control Register */
1552 #define Smart_SMR1 __PORT8 0xFFFF80 /* Serial Mode Register 1 */
1553 #define SCI_BRR1 __PORT8 0xFFFF81 /* Bit Rate Register 1 */
1554 #define Smart_BRR1 __PORT8 0xFFFF81 /* Bit Rate Register 1 */
1555 #define IIC_ICSR1 __PORT8 0xFFFF81 /* I2C Bus Status Register */
1556 #define SCI_SCR1 __PORT8 0xFFFF82 /* Serial Control Register 1 */
1557 #define SCR1_CKE0m 0x01
1558 #define SCR1_CKE1m 0x02
1559 #define SCR1_TEIEm 0x04
1560 #define SCR1_MPIEm 0x08
1561 #define SCR1_REm 0x10
1562 #define SCR1_TEm 0x20
1563 #define SCR1_RIEm 0x40
1564 #define SCR1_TIEm 0x80
1565 #define Smart_SCR1 __PORT8 0xFFFF82 /* Serial Control Register 1 */
1566 #define SCI_TDR1 __PORT8 0xFFFF83 /* Transmit Data Register 1 */
1567 #define Smart_TDR1 __PORT8 0xFFFF83 /* Transmit Data Register 1 */
1568 #define SCI_SSR1 __PORT8 0xFFFF84 /* Serial Status Register 1 */
1569 #define SSR1_MPBTm 0x01
1570 #define SSR1_MPBm 0x02
1571 #define SSR1_TENDm 0x04
1572 #define SSR1_PERm 0x08
1573 #define SSR1_FERm 0x10
1574 #define SSR1_ORERm 0x20
1575 #define SSR1_RDRFm 0x40
1576 #define SSR1_TDREm 0x80
1577 #define Smart_SSR1 __PORT8 0xFFFF84 /* Serial Status Register 1 */
1578 #define SCI_RDR1 __PORT8 0xFFFF85 /* Receive Data Register 1 */
1579 #define Smart_RDR1 __PORT8 0xFFFF85 /* Receive Data Register 1 */
1580 #define SCI_SCMR1 __PORT8 0xFFFF86 /* Smart Card Mode Register 1 */
1581 #define SCMR1_SMIFm 0x01
1582 #define SCMR1_SINVm 0x04
1583 #define SCMR1_SDIRm 0x08
1584 #define IIC_ICDR1 __PORT8 0xFFFF86 /* I2C Bus Data Register */
1585 #define IIC_SARX1 __PORT8 0xFFFF86 /* 2nd Slave Address Register */
1586 #define IIC_ICMR1 __PORT8 0xFFFF87 /* -I2C Bus Mode Register */
1587 #define ICMR1_BC0FSm 0x01
1588 #define ICMR1_BC1m 0x02
1589 #define ICMR1_BC2m 0x04
1590 #define ICMR1_CKS0m 0x08
1591 #define ICMR1_CKS1m 0x10
1592 #define ICMR1_CKS2m 0x20
1593 #define ICMR1_WAITm 0x40
1594 #define ICMR1_MLSm 0x80
1595 #define IIC_SAR1 __PORT8 0xFFFF87 /* Slave Address Register */
1596 #define SCI_SMR2 __PORT8 0xFFFF88 /* Serial Mode Register 2 */
1597 #define SMR2_CKS0m 0x01
1598 #define SMR2_CKS1m 0x02
1599 #define SMR2_MPm 0x04
1600 #define SMR2_STOPm 0x08
1601 #define SMR2_OEm 0x10
1602 #define SMR2_PEm 0x20
1603 #define SMR2_CHRm 0x40
1604 #define SMR2_CAm 0x80
1605 #define Smart_SMR2 __PORT8 0xFFFF88 /* Serial Mode Register 2 */
1606 #define SCI_BRR2 __PORT8 0xFFFF89 /* Bit Rate Register 2 */
1607 #define Smart_BRR2 __PORT8 0xFFFF89 /* Bit Rate Register 2 */
1608 #define SCI_SCR2 __PORT8 0xFFFF8A /* Serial Control Register 2 */
1609 #define SCR2_CKE0m 0x01
1610 #define SCR2_CKE1m 0x02
1611 #define SCR2_TEIEm 0x04
1612 #define SCR2_MPIEm 0x08
1613 #define SCR2_REm 0x10
1614 #define SCR2_TEm 0x20
1615 #define SCR2_RIEm 0x40
1616 #define SCR2_TIEm 0x80
1617 #define Smart_SCR2 __PORT8 0xFFFF8A /* Serial Control Register 2 */
1618 #define SCI_TDR2 __PORT8 0xFFFF8B /* Transmit Data Register 2 */
1619 #define Smart_TDR2 __PORT8 0xFFFF8B /* Transmit Data Register 2 */
1620 #define SCI_SSR2 __PORT8 0xFFFF8C /* Serial Status Register 2 */
1621 #define SSR2_MPBTm 0x01
1622 #define SSR2_MPBm 0x02
1623 #define SSR2_TENDm 0x04
1624 #define SSR2_PERm 0x08
1625 #define SSR2_FERm 0x10
1626 #define SSR2_ORERm 0x20
1627 #define SSR2_RDRFm 0x40
1628 #define SSR2_TDREm 0x80
1629 #define Smart_SSR2 __PORT8 0xFFFF8C /* Serial Status Register 2 */
1630 #define SCI_RDR2 __PORT8 0xFFFF8D /* Receive Data Register 2 */
1631 #define SCI_SCMR2 __PORT8 0xFFFF8E /* Smart Card Mode Register 2 */
1632 #define SCI_SCMR2 __PORT8 0xFFFF8E /* Smart Card Mode Register 2 */
1633 #define SCMR2_SMIFm 0x01
1634 #define SCMR2_SINVm 0x04
1635 #define SCMR2_SDIRm 0x08
1637 /* Module A/D Converter */
1638 #define AD_ADDRAH __PORT8 0xFFFF90 /* AD Data Register AH */
1639 #define ADDRAH_AD2m 0x01
1640 #define ADDRAH_AD3m 0x02
1641 #define ADDRAH_AD4m 0x04
1642 #define ADDRAH_AD5m 0x08
1643 #define ADDRAH_AD6m 0x10
1644 #define ADDRAH_AD7m 0x20
1645 #define ADDRAH_AD8m 0x40
1646 #define ADDRAH_AD9m 0x80
1647 #define AD_ADDRAL __PORT8 0xFFFF91 /* AD Data Register AL*/
1648 #define ADDRAL_AD0m 0x40
1649 #define ADDRAL_AD1m 0x80
1650 #define AD_ADDRBH __PORT8 0xFFFF92 /* AD Data Register BH*/
1651 #define ADDRBH_AD2m 0x01
1652 #define ADDRBH_AD3m 0x02
1653 #define ADDRBH_AD4m 0x04
1654 #define ADDRBH_AD5m 0x08
1655 #define ADDRBH_AD6m 0x10
1656 #define ADDRBH_AD7m 0x20
1657 #define ADDRBH_AD8m 0x40
1658 #define ADDRBH_AD9m 0x80
1659 #define AD_ADDRBL __PORT8 0xFFFF93 /* AD Data Register BL*/
1660 #define ADDRBL_AD0m 0x40
1661 #define ADDRBL_AD1m 0x80
1662 #define AD_ADDRCH __PORT8 0xFFFF94 /* AD Data Register CH */
1663 #define ADDRCH_AD2m 0x01
1664 #define ADDRCH_AD3m 0x02
1665 #define ADDRCH_AD4m 0x04
1666 #define ADDRCH_AD5m 0x08
1667 #define ADDRCH_AD6m 0x10
1668 #define ADDRCH_AD7m 0x20
1669 #define ADDRCH_AD8m 0x40
1670 #define ADDRCH_AD9m 0x80
1671 #define AD_ADDRCL __PORT8 0xFFFF95 /* AD Data Register CH */
1672 #define ADDRCL_AD0m 0x40
1673 #define ADDRCL_AD1m 0x80
1674 #define AD_ADDRDH __PORT8 0xFFFF96 /* AD Data Register DH */
1675 #define ADDRDH_AD2m 0x01
1676 #define ADDRDH_AD3m 0x02
1677 #define ADDRDH_AD4m 0x04
1678 #define ADDRDH_AD5m 0x08
1679 #define ADDRDH_AD6m 0x10
1680 #define ADDRDH_AD7m 0x20
1681 #define ADDRDH_AD8m 0x40
1682 #define ADDRDH_AD9m 0x80
1683 #define AD_ADDRDL __PORT8 0xFFFF97 /* AD Data Register DL */
1684 #define ADDRDL_AD0m 0x40
1685 #define ADDRDL_AD1m 0x80
1686 #define AD_ADCSR __PORT8 0xFFFF98 /* AD ControlStatus Register */
1687 #define ADCSR_CH0m 0x01
1688 #define ADCSR_CH1m 0x02
1689 #define ADCSR_CH2m 0x04
1690 #define ADCSR_CH3m 0x08
1691 #define ADCSR_SCANm 0x10
1692 #define ADCSR_ADSTm 0x20
1693 #define ADCSR_ADIEm 0x40
1694 #define ADCSR_ADFm 0x80
1695 #define AD_ADCR __PORT8 0xFFFF99 /* AD Control Register */
1696 #define ADCR_CKS0m 0x04
1697 #define ADCR_CKS1m 0x08
1698 #define ADCR_TRGS0m 0x40
1699 #define ADCR_TRGS1m 0x80
1701 #define TMR_TCSR1 __PORT8 0xFFFFA2 /* (R/W) Timer ControlStatus Register 1 */
1702 #define TCSR1_CKS0m 0x01
1703 #define TCSR1_CKS1m 0x02
1704 #define TCSR1_CKS2m 0x04
1705 #define TCSR1_OVFm 0x80
1706 #define TMR_TCNT1 __PORT8 0xFFFFA3 /* (R) Timer Counter 1 */
1707 /* Module A/D Converter */
1708 #define DA_DADR0 __PORT8 0xFFFFA4 /* DA Data Register 0 */
1709 #define DA_DADR1 __PORT8 0xFFFFA5 /* DA Data Register 1 */
1710 #define DA_DACR01 __PORT8 0xFFFFA6 /* DA Control Register 01 */
1711 #define DACR01_DAEm 0x20
1712 #define DACR01_DAOE0m 0x40
1713 #define DACR01_DAOE1m 0x80
1714 /* Module Flash Memory */
1715 #define FLM_FLMCR1 __PORT8 0xFFFFA8 /* Flash Memory Control Register 1 */
1716 #define FLMCR1_Pm 0x01 /* Transition to program mode */
1717 #define FLMCR1_Em 0x02 /* Transition to erase mode */
1718 #define FLMCR1_PVm 0x04 /* Transition to program-verify mode */
1719 #define FLMCR1_EVm 0x08 /* Transition to erase-verify mode */
1720 #define FLMCR1_PSUm 0x10 /* Program setup when FWE = 1 and SWE1 = 1*/
1721 #define FLMCR1_ESUm 0x20 /* Erase setup when FWE = 1 and SWE1 = 1 */
1722 #define FLMCR1_SWEm 0x40 /* 1= enable writes when FWE=1 */
1723 #define FLMCR1_FWEm 0x80 /* 1 = programming enabled by FWE pin */
1724 #define FLM_FLMCR2 __PORT8 0xFFFFA9 /* Flash Memory Control Register 2 */
1725 #define FLMCR2_FLERm 0x80 /* Flash memory modification error */
1726 #define FLM_EBR1 __PORT8 0xFFFFAA /* Erase Block Register 1 */
1727 #define EBR1_EB0m 0x01 /* Selects block to erase */
1728 #define EBR1_EB1m 0x02
1729 #define EBR1_EB2m 0x04
1730 #define EBR1_EB3m 0x08
1731 #define EBR1_EB4m 0x10
1732 #define EBR1_EB5m 0x20
1733 #define EBR1_EB6m 0x40
1734 #define EBR1_EB7m 0x80
1735 #define FLM_EBR2 __PORT8 0xFFFFAB /* Erase Block Register 2 */
1736 #define EBR2_EB8m 0x01
1737 #define EBR2_EB9m 0x02
1738 #define EBR2_EB10m 0x04
1739 #define EBR2_EB11m 0x08
1740 #define EBR2_EB12m 0x10 /* Valid on the H8S/2630. On the H8S/2638 and H8S/2639 these bits are reserved and only 0 */
1741 #define EBR2_EB13m 0x20 /* Valid on the H8S/2630. On the H8S/2638 and H8S/2639 these bits are reserved and only 0 */
1742 #define FLM_FLPWCR __PORT8 0xFFFFAC /* Flash Memory Power Control Register */
1743 #define FLPWCR_PDWNDm 0x80
1745 #define DIO_PORT1 __PORT8 0xFFFFB0 /* DIO 1 Register */
1746 #define PORT1_P10m 0x01
1747 #define PORT1_P11m 0x02
1748 #define PORT1_P12m 0x04
1749 #define PORT1_P13m 0x08
1750 #define PORT1_P14m 0x10
1751 #define PORT1_P15m 0x20
1752 #define PORT1_P16m 0x40
1753 #define PORT1_P17m 0x80
1754 #define DIO_PORT3 __PORT8 0xFFFFB2 /* DIO 3 Register */
1755 #define PORT3_P30m 0x01
1756 #define PORT3_P31m 0x02
1757 #define PORT3_P32m 0x04
1758 #define PORT3_P33m 0x08
1759 #define PORT3_P34m 0x10
1760 #define PORT3_P35m 0x20
1761 #define DIO_PORT4 __PORT8 0xFFFFB3 /* DIO 4 Register */
1762 #define PORT4_P40m 0x01
1763 #define PORT4_P41m 0x02
1764 #define PORT4_P42m 0x04
1765 #define PORT4_P43m 0x08
1766 #define PORT4_P44m 0x10
1767 #define PORT4_P45m 0x20
1768 #define PORT4_P46m 0x40
1769 #define PORT4_P47m 0x80
1770 #define DIO_PORT9 __PORT8 0xFFFFB8 /* DIO 9 Register */
1771 #define PORT9_P90m 0x01
1772 #define PORT9_P91m 0x02
1773 #define PORT9_P92m 0x04
1774 #define PORT9_P93m 0x08
1775 #define DIO_PORTA __PORT8 0xFFFFB9 /* DIO A Register */
1776 #define PORTA_PA0m 0x01
1777 #define PORTA_PA1m 0x02
1778 #define PORTA_PA2m 0x04
1779 #define PORTA_PA3m 0x08
1780 #define DIO_PORTB __PORT8 0xFFFFBA /* DIO B Register */
1781 #define PORTB_PB0m 0x01
1782 #define PORTB_PB1m 0x02
1783 #define PORTB_PB2m 0x04
1784 #define PORTB_PB3m 0x08
1785 #define PORTB_PB4m 0x10
1786 #define PORTB_PB5m 0x20
1787 #define PORTB_PB6m 0x40
1788 #define PORTB_PB7m 0x80
1789 #define DIO_PORTC __PORT8 0xFFFFBB /* DIO C Register */
1790 #define PORTC_PC0m 0x01
1791 #define PORTC_PC1m 0x02
1792 #define PORTC_PC2m 0x04
1793 #define PORTC_PC3m 0x08
1794 #define PORTC_PC4m 0x10
1795 #define PORTC_PC5m 0x20
1796 #define PORTC_PC6m 0x40
1797 #define PORTC_PC7m 0x80
1798 #define DIO_PORTD __PORT8 0xFFFFBC /* DIO D Register */
1799 #define PORTD_PD0m 0x01
1800 #define PORTD_PD1m 0x02
1801 #define PORTD_PD2m 0x04
1802 #define PORTD_PD3m 0x08
1803 #define PORTD_PD4m 0x10
1804 #define PORTD_PD5m 0x20
1805 #define PORTD_PD6m 0x40
1806 #define PORTD_PD7m 0x80
1807 #define DIO_PORTE __PORT8 0xFFFFBD /* DIO E Register */
1808 #define PORTE_PE0m 0x01
1809 #define PORTE_PE1m 0x02
1810 #define PORTE_PE2m 0x04
1811 #define PORTE_PE3m 0x08
1812 #define PORTE_PE4m 0x10
1813 #define PORTE_PE5m 0x20
1814 #define PORTE_PE6m 0x40
1815 #define PORTE_PE7m 0x80
1816 #define DIO_PORTF __PORT8 0xFFFFBE /* DIO F Register */
1817 #define PORTF_PF0m 0x01
1818 #define PORTF_PF3m 0x08
1819 #define PORTF_PF4m 0x10
1820 #define PORTF_PF5m 0x20
1821 #define PORTF_PF6m 0x40
1822 #define PORTF_PF7m 0x80
1824 // aditional definition
1827 #define IIC_SCRX __PORT8 0xFFFDB4 /* Serial Control Register X */
1828 #define SCRX_FLSHEm 0x08
1829 #define SCRX_IICEm 0x10
1830 #define SCRX_IICX0m 0x20
1831 #define SCRX_IICX1m 0x40
1834 #define SYS_LPWRCR __PORT8 0xFFFDEC /* Low-Power Control Register */
1835 #define LPWRCR_STC0m 0x01 /* */
1836 #define LPWRCR_STC1m 0x02
1837 #define LPWRCR_STCxm 0x03
1838 #define LPWRCR_RFCUTm 0x08
1839 #define LPWRCR_SUBSTPm 0x10
1840 #define LPWRCR_NESELm 0x20
1841 #define LPWRCR_LSONm 0x40
1842 #define LPWRCR_DTONm 0x80
1846 /* define serial control registers */
1847 #define SCI_SMR2 __PORT8 0xFFFF88 /* Serial Mode Register 2 */
1848 #define SMR2_CKS0m 0x01
1849 #define SMR2_CKS1m 0x02
1850 #define SMR2_MPm 0x04
1851 #define SMR2_STOPm 0x08
1852 #define SMR2_OEm 0x10
1853 #define SMR2_PEm 0x20
1854 #define SMR2_CHRm 0x40
1855 #define SMR2_CAm 0x80
1856 #define SCI_BRR2 __PORT8 0xFFFF89 /* Bit Rate Register 2 */
1857 #define SCI_SCR2 __PORT8 0xFFFF8A /* Serial Control Register 2 */
1858 #define SCR2_CKE0m 0x01
1859 #define SCR2_CKE1m 0x02
1860 #define SCR2_TEIEm 0x04
1861 #define SCR2_MPIEm 0x08
1862 #define SCR2_REm 0x10
1863 #define SCR2_TEm 0x20
1864 #define SCR2_RIEm 0x40
1865 #define SCR2_TIEm 0x80
1866 #define SCI_TDR2 __PORT8 0xFFFF8B /* Transmit Data Register 2 */
1867 #define SCI_SSR2 __PORT8 0xFFFF8C /* Serial Status Register 2 */
1868 #define SSR2_MPBTm 0x01
1869 #define SSR2_MPBm 0x02
1870 #define SSR2_TENDm 0x04
1871 #define SSR2_PERm 0x08
1872 #define SSR2_FERm 0x10
1873 #define SSR2_ORERm 0x20
1874 #define SSR2_RDRFm 0x40
1875 #define SSR2_TDREm 0x80
1876 #define SCI_RDR2 __PORT8 0xFFFF8D /* Receive Data Register 2 */
1877 #define SCI_SCMR2 __PORT8 0xFFFF8E /* Smart Card Mode Register 2 */
1878 #define SCMR2_SMIFm 0x01
1879 #define SCMR2_SINVm 0x04
1880 #define SCMR2_SDIRm 0x08
1881 /* END define serial control registers */
1884 /* Module Stop Control Register */
1885 #define SYS_MSTPCRA __PORT8 0xFFFDE8 /* Module Stop Control Register A */
1886 #define MSTPCRA_MSTPA0m 0x01
1887 #define MSTPCRA_MSTPA1m 0x02
1888 #define MSTPCRA_ADCm 0x02
1889 #define MSTPCRA_MSTPA2m 0x04
1890 #define MSTPCRA_DA01m 0x04
1891 #define MSTPCRA_MSTPA3m 0x08
1892 #define MSTPCRA_PPGm 0x08
1893 #define MSTPCRA_MSTPA4m 0x10
1894 #define MSTPCRA_MSTPA5m 0x20
1895 #define MSTPCRA_TPUm 0x20
1896 #define MSTPCRA_MSTPA6m 0x40
1897 #define MSTPCRA_DTCm 0x40
1898 #define MSTPCRA_MSTPA7m 0x80
1899 #define SYS_MSTPCRB __PORT8 0xFFFDE9 /* Module Stop Control Register B */
1900 #define MSTPCRB_MSTPB0m 0x01
1901 #define MSTPCRB_MSTPB1m 0x02
1902 #define MSTPCRB_MSTPB2m 0x04
1903 #define MSTPCRB_MSTPB3m 0x08
1904 #define MSTPCRB_IIC1m 0x08
1905 #define MSTPCRB_MSTPB4m 0x10
1906 #define MSTPCRB_IIC0m 0x10
1907 #define MSTPCRB_MSTPB5m 0x20
1908 #define MSTPCRB_SCI2m 0x20
1909 #define MSTPCRB_MSTPB6m 0x40
1910 #define MSTPCRB_SCI1m 0x40
1911 #define MSTPCRB_MSTPB7m 0x80
1912 #define MSTPCRB_SCI0m 0x80
1913 #define SYS_MSTPCRC __PORT8 0xFFFDEA /* Module Stop Control Register C */
1914 #define MSTPCRC_MSTPC0m 0x01
1915 #define MSTPCRC_MSTPC1m 0x02
1916 #define MSTPCRC_MSTPC2m 0x04
1917 #define MSTPCRC_HCAN1m 0x04
1918 #define MSTPCRC_MSTPC3m 0x08
1919 #define MSTPCRC_HCAN0m 0x08
1920 #define MSTPCRC_MSTPC4m 0x10
1921 #define MSTPCRC_PBCm 0x10
1922 #define MSTPCRC_MSTPC5m 0x20
1923 #define MSTPCRC_MSTPC6m 0x40
1924 #define MSTPCRC_SCI4m 0x40
1925 #define MSTPCRC_MSTPC7m 0x80
1926 #define MSTPCRC_SCI3m 0x80
1927 #define SYS_MSTPCRD __PORT8 0xFFFC60 /* Module Stop Control Register D */
1928 #define MSTPCRD_MSTPD7m 0x80
1929 #define MSTPCRD_PWMm 0x80
1930 /* END Module Stop Control Register */
1932 /* start Flash register compatibility with 2633 programs (only different names of existing FLMCR1 bits)*/ /* // comented are the same */
1933 //#define FLM_FLMCR1 __PORT8 0xFFFFA8 /* Flash Memory Control Register 1 */
1934 #define FLMCR1_P1m 0x01 /* Transition to program mode */
1935 #define FLMCR1_E1m 0x02 /* Transition to erase mode */
1936 #define FLMCR1_PV1m 0x04 /* Transition to program-verify mode */
1937 #define FLMCR1_EV1m 0x08 /* Transition to erase-verify mode */
1938 #define FLMCR1_PSU1m 0x10 /* Program setup when FWE = 1 and SWE1 = 1*/
1939 #define FLMCR1_ESU1m 0x20 /* Erase setup when FWE = 1 and SWE1 = 1 */
1940 #define FLMCR1_SWE1m 0x40 /* 1= enable writes when FWE=1 */
1941 //#define FLMCR1_FWEm 0x80 /* 1 = programming enabled by FWE pin */
1942 //#define FLM_FLMCR2 __PORT8 0xFFFFA9 /* Flash Memory Control Register 2 */
1943 //#define FLMCR2_FLERm 0x80 /* Flash memory modification error */
1944 /* end Flash register compatibility with 2633 (only different names of FLMCR1 bits)*/
1946 /* exception vectors numbers */ // nechat schvalit !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1948 #define EXCPTVEC_POWRES 0
1949 #define EXCPTVEC_MANRES 1
1950 #define EXCPTVEC_TRACE 5
1951 #define EXCPTVEC_DIRTRANS 6
1952 #define EXCPTVEC_NMI 7
1953 #define EXCPTVEC_TRAP0 8
1954 #define EXCPTVEC_TRAP1 9
1955 #define EXCPTVEC_TRAP2 10
1956 #define EXCPTVEC_TRAP3 11
1957 #define EXCPTVEC_IRQ0 16
1958 #define EXCPTVEC_IRQ1 17
1959 #define EXCPTVEC_IRQ2 18
1960 #define EXCPTVEC_IRQ3 19
1961 #define EXCPTVEC_IRQ4 20
1962 #define EXCPTVEC_IRQ5 21
1963 #define EXCPTVEC_IRQ6 22
1964 #define EXCPTVEC_IRQ7 23
1965 #define EXCPTVEC_SWDEND 24
1966 #define EXCPTVEC_WOVI0 25
1967 #define EXCPTVEC_CMI 26
1968 #define EXCPTVEC_PBC 27
1969 #define EXCPTVEC_ADI 28
1970 #define EXCPTVEC_WOVI1 29
1971 #define EXCPTVEC_TGI0A 32 /* TPU 0 */
1972 #define EXCPTVEC_TGI0B 33
1973 #define EXCPTVEC_TGI0C 34
1974 #define EXCPTVEC_TGI0D 35
1975 #define EXCPTVEC_TCI0V 36
1976 #define EXCPTVEC_TGI1A 40 /* TPU 1 */
1977 #define EXCPTVEC_TGI1B 41
1978 #define EXCPTVEC_TCI1V 42
1979 #define EXCPTVEC_TCI1U 43
1980 #define EXCPTVEC_TGI2A 44 /* TPU 2 */
1981 #define EXCPTVEC_TGI2B 45
1982 #define EXCPTVEC_TCI2V 46
1983 #define EXCPTVEC_TCI2U 47
1984 #define EXCPTVEC_TGI3A 48 /* TPU 3 */
1985 #define EXCPTVEC_TGI3B 49
1986 #define EXCPTVEC_TGI3C 50
1987 #define EXCPTVEC_TGI3D 51
1988 #define EXCPTVEC_TCI3V 52
1989 #define EXCPTVEC_TGI4A 56 /* TPU 4 */
1990 #define EXCPTVEC_TGI4B 57
1991 #define EXCPTVEC_TCI4V 58
1992 #define EXCPTVEC_TCI4U 59
1993 #define EXCPTVEC_TGI5A 60 /* TPU 5 */
1994 #define EXCPTVEC_TGI5B 61
1995 #define EXCPTVEC_TCI5V 62
1996 #define EXCPTVEC_TCI5U 63
1997 #define EXCPTVEC_CMIA0 64 /* 8 bit tim 0 */
1998 #define EXCPTVEC_CMIB0 65
1999 #define EXCPTVEC_OVI0 66
2000 #define EXCPTVEC_CMIA1 68 /* 8 bit tim 1 */
2001 #define EXCPTVEC_CMIB1 69
2002 #define EXCPTVEC_OVI1 70
2003 #define EXCPTVEC_DEND0A 72 /* DMAC */
2004 #define EXCPTVEC_DEND0B 73
2005 #define EXCPTVEC_DEND1A 74
2006 #define EXCPTVEC_DEND1B 75
2007 #define EXCPTVEC_ERI0 80 /* SCI 0 */
2008 #define EXCPTVEC_RXI0 81
2009 #define EXCPTVEC_TXI0 82
2010 #define EXCPTVEC_TEI0 83
2011 #define EXCPTVEC_ERI1 84 /* SCI 1 */
2012 #define EXCPTVEC_RXI1 85
2013 #define EXCPTVEC_TXI1 86
2014 #define EXCPTVEC_TEI1 87
2015 #define EXCPTVEC_ERI2 88 /* SCI 2 */
2016 #define EXCPTVEC_RXI2 89
2017 #define EXCPTVEC_TXI2 90
2018 #define EXCPTVEC_TEI2 91
2019 #define EXCPTVEC_CMIA2 92 /* 8 bit tim 2 */
2020 #define EXCPTVEC_CMIB2 93
2021 #define EXCPTVEC_OVI2 94
2022 #define EXCPTVEC_CMIA3 96 /* 8 bit tim 3 */
2023 #define EXCPTVEC_CMIB3 97
2024 #define EXCPTVEC_OVI3 98
2025 #define EXCPTVEC_IICI0 100 /* IIC 0 */
2026 #define EXCPTVEC_DDCSW1 101
2027 #define EXCPTVEC_IICI1 102 /* IIC 1 */
2028 #define EXCPTVEC_ERI3 120 /* SCI 3 */
2029 #define EXCPTVEC_RXI3 121
2030 #define EXCPTVEC_TXI3 122
2031 #define EXCPTVEC_TEI3 123
2032 #define EXCPTVEC_ERI4 124 /* SCI 4 */
2033 #define EXCPTVEC_RXI4 125
2034 #define EXCPTVEC_TXI4 126
2035 #define EXCPTVEC_TEI4 127
2037 /* Timer control register (TPCR) */
2038 #define TPCR_TPSCm 0x07 /* Clock sources */
2039 #define TPCR_TPSC_F1 0x00 /* fi clock/1 */
2040 #define TPCR_TPSC_F4 0x01 /* fi clock/4 */
2041 #define TPCR_TPSC_F16 0x02 /* fi clock/16 */
2042 #define TPCR_TPSC_F64 0x03 /* fi clock/64 */
2043 #define TPCR_TPSC_CA 0x04 /* TCLKA */
2044 #define TPCR_TPSC_012CB 0x05 /* TCLKB (only 012) */
2045 #define TPCR_TPSC_02CC 0x06 /* TCLKC (only 02) */
2046 #define TPCR_TPSC_45CC 0x05 /* TCLKC (only 45) */
2047 #define TPCR_TPSC_05CD 0x07 /* TCLKD (only 05) */
2048 #define TPCR_TPSC_135F256 0x06 /* fi clock/256 (only 135) */
2049 #define TPCR_TPSC_234F1024 0x05 /* fi clock/1024 (only 234) */
2050 #define TPCR_TPSC_3F4096 0x007 /* fi clock/4096 (only 3) */
2051 #define TPCR_CKEGm 0x018 /* Clock edge */
2052 #define TPCR_CKEG_RIS 0x000 /* Rising edge */
2053 #define TPCR_CKEG_FAL 0x008 /* Falling edge */
2054 #define TPCR_CKEG_BOTH 0x018 /* Both edges */
2055 #define TPCR_CCLRm 0xe0 /* Counter clearing source */
2056 #define TPCR_CCLR_DIS 0x00 /* disabled */
2057 #define TPCR_CCLR_TGRA 0x20 /* source TGRA compare match/input capture */
2058 #define TPCR_CCLR_TGRB 0x40 /* source TGRB compare match/input capture */
2059 #define TPCR_CCLR_SYNC 0x60 /* synchronous clear by TSYR_SYNC */
2060 #define TPCR_CCLR_TGRC 0xa0 /* source TGRC compare match/input capture */
2061 #define TPCR_CCLR_TGRD 0xc0 /* source TGRD compare match/input capture */
2063 /* Timer mode register (TMDR) */
2064 #define TPMDR_MDm 0x0f /* timer operating mode */
2065 #define TPMDR_MD_NORMAL 0x00 /* normal */
2066 #define TPMDR_MD_PWM1 0x02 /* PWM 1 */
2067 #define TPMDR_MD_PWM2 0x03 /* PWM 2 */
2068 #define TPMDR_MD_PHACN1 0x04 /* phase counting 1 (only 1245) */
2069 #define TPMDR_MD_PHACN2 0x05 /* phase counting 2 (only 1245) */
2070 #define TPMDR_MD_PHACN3 0x06 /* phase counting 3 (only 1245) */
2071 #define TPMDR_MD_PHACN4 0x07 /* phase counting 4 (only 1245) */
2072 #define TPMDR_BFAm 0x10 /* TGRA, TGRC together for buffer operation */
2073 #define TPMDR_BFBm 0x20 /* TGRB, TGRD together for buffer operation */
2075 #endif /* _H82639H_H */