1 /* procesor H8S/2638 ver 1.1 */
5 #include <system_def.h>
9 #ifdef XRAM_SUPPORT_ENABLED
10 #define FULL_XRAM_ADRBUS
11 #endif /*XRAM_SUPPORT_ENABLED*/
12 #define SMALL_ADRBUS 8
14 static void deb_led_out(char val)
34 /* Provided by linker script */
35 extern char __boot_fn_load;
36 extern char __boot_fn_start;
37 extern char __boot_fn_end;
39 static void relocate_boot_fn()
41 size_t reloc_size=&__boot_fn_end-&__boot_fn_start;
43 if(&__boot_fn_load != &__boot_fn_start) {
44 memcpy(&__boot_fn_start,&__boot_fn_load,reloc_size);
52 #if 1 /* registers setup */
53 /* Internal RAM enabled, advanced interrupt mode */
54 /* *SYS_SYSCR = 1*SYSCR_RAMEm | 1*SYSCR_INTM1m ; */
56 /* Remap 4kB of RAM from 0xffd000-0xffdfff to 0x0-0xfff */
57 /* *FLM_RAMER= 1*RAMER_RAMSm | 0&RAMER_RAMxm */
58 /* Sideefect - sets Flash software protection */
60 /* Enables access to flash control registers */
61 *IIC_SCRX |= SCRX_FLSHEm;
63 /* set shadow registers */
75 /* show something on debug leds */
79 /* SHADOW_REG_SET(DIO_P1DDR,0x03); /\* A20 and A21 are outputs *\/ */
81 *DIO_P3DR=0x09; /* Inactive value of TxD0 and TxD1 has to be log 1 */
82 SHADOW_REG_SET(DIO_P3DDR,0x09); /* TxD0 and TxD1 to outputs */
83 *DIO_PADR=0x02; /* Inactive value of TxD2 has to be log 1 */
84 SHADOW_REG_SET(DIO_PADDR,0x02); /* TxD0 and TxD1 to outputs */
86 /* Setup system clock oscilator */
88 /* *SYS_LPWRCR=2&LPWRCR_STCxm; */
90 /* *SYS_LPWRCR=1&LPWRCR_STCxm; */
92 #if (CPU_SYS_HZ != CPU_REF_HZ) && (CPU_SYS_HZ/2 != CPU_REF_HZ) && (CPU_SYS_HZ/4 != CPU_REF_HZ)
93 #error Wrong clock settings: CPU_SYS_HZ must be 1, 2 or 4 multiple of CPU_REF_HZ
95 #if CPU_SYS_HZ > 20000000
96 #error Wrong clock settings: CPU_SYS_HZ must be less or equal to 20000000
98 const char clkrat2stc[]={0,0/*1*/,1/*2*/,1,2/*4*/,2,2,2,3/*8*/};
99 *SYS_LPWRCR=LPWRCR_STCxm&(LPWRCR_STC0m*
100 clkrat2stc[(CPU_SYS_HZ+CPU_REF_HZ/2)/CPU_REF_HZ]);
105 /* No clock disable, immediate change, busmaster high-speed */
106 *SYS_SCKCR=(0*SCKCR_PSTOPm)|(1*SCKCR_STCSm)|(0&SCKCR_SCKxm);
109 /* Setup chipselect outputs CS4 CS5 CS6 */
111 SHADOW_REG_SET(DIO_P7DDR,1|2|4);
113 // SHADOW_REG_SET(DIO_P7DDR,0); not on 2638
116 /* Setup chipselect outputs CS3 CS2 CS1 CS0 */
117 // *DIO_PGDR |=2|4|8|0x10; no on 2638
119 SHADOW_REG_SET(DIO_PGDDR,2|4|8|0x10);
121 // SHADOW_REG_SET(DIO_PGDDR,2|4); no on 2638
125 /* setup chipselect 0 - FLASH */
126 *BUS_ABWCR&=~ABWCR_ABW0m; /* 16 bit width */
127 *BUS_ASTCR&=~ASTCR_AST0m; /* 2 states access */
128 //*BUS_ASTCR|=ASTCR_AST0m; /* 3 states access EDK 2638 */
129 *BUS_WCRL&=~(WCRL_W01m|WCRL_W00m);/* 0 additional wait states */
131 /* setup chipselect 1 - XRAM */
132 *BUS_ABWCR&=~ABWCR_ABW1m; /* 16 bit width */
133 *BUS_ASTCR&=~ASTCR_AST1m; /* 2 states access */
134 *BUS_WCRL&=~(WCRL_W11m|WCRL_W10m);/* 0 additional wait states */
136 /* setup chipselect 2 - USB */
137 *BUS_ABWCR|=ABWCR_ABW2m; /* 8 bit width */
138 *BUS_ASTCR|=ASTCR_AST2m; /* 3 states access */
139 *BUS_WCRL&=~(WCRL_W21m|WCRL_W20m);/* 0 additional wait states */
140 *BUS_WCRL|=1*WCRL_W21m; /* 0/1 additional wait state */
142 /* setup chipselect 3 - KBD */
143 *BUS_ABWCR|=ABWCR_ABW3m; /* 8 bit width */
144 *BUS_ASTCR|=ASTCR_AST3m; /* 3 states access */
145 *BUS_WCRL|=(WCRL_W31m|WCRL_W30m);/* 0 additional wait states */
149 /* setup chipselect 4 - IDE */
150 *BUS_ABWCR&=~ABWCR_ABW4m; /* 16 bit width */
151 *BUS_ASTCR|=ASTCR_AST4m; /* 3 states access */
152 *BUS_WCRH&=~(WCRH_W41m|WCRH_W40m);/* 0 additional wait states */
154 /* setup chipselect 5 - IDE */
155 *BUS_ABWCR&=~ABWCR_ABW5m; /* 16 bit width */
156 *BUS_ASTCR|=ASTCR_AST5m; /* 3 states access */
157 *BUS_WCRH&=~(WCRH_W51m|WCRH_W50m);/* 0 additional wait states */
159 /* setup chipselect 6 - KL41 */
160 *BUS_ABWCR|=ABWCR_ABW6m; /* 8 bit width */
161 *BUS_ASTCR|=ASTCR_AST6m; /* 3 states access */
162 *BUS_WCRH=WCRH_W61m|WCRH_W60m; /* 3 additional wait states */
169 /* cross cs wait| rd/wr wait | no burst and DRAM */
170 *BUS_BCRH=0*BCRH_ICIS1m | 0*BCRH_ICIS0m;
171 /* release | no DMAC buffer | no external wait */
172 *BUS_BCRL=0*BCRL_WDBEm; // 0*BCRL_BRLEm | 0*BCRL_WDBEm | 0*BCRL_WAITEm; BRLE and WAITE not build in 2638
173 *DIO_PCDDR=0xff; /* A0-A7 are outputs */
175 *DIO_PBDDR=0xff; /* A8-A15 are outputs */
176 #endif /*SMALL_ADRBUS*/
177 #ifndef FULL_XRAM_ADRBUS
179 *SYS_PFCR=__val2mfld(PFCR_AExm,16-8); /* only 16 address lines */
180 #else /*SMALL_ADRBUS*/
181 *SYS_PFCR=__val2mfld(PFCR_AExm,SMALL_ADRBUS-8); /* only SMALL_ADRBUS address lines */
182 #endif /*SMALL_ADRBUS*/
183 #endif /* FULL_XRAM_ADRBUS */
185 #endif /* registers setup */
189 #ifdef FULL_XRAM_ADRBUS
190 /* Setup full 22 address lines */
192 *DIO_PADDR=0x0f; /* A16-A19 are outputs */
193 /* number of address output signals */
194 *SYS_PFCR=__val2mfld(PFCR_AExm,22-8);
195 #endif /*FULL_XRAM_ADRBUS*/