arch/arm/mach-at91sam7/defines/lib_AT91SAM7XC256.h

   1 /* ----------------------------------------------------------------------------
   2  *         ATMEL Microcontroller Software Support  -  ROUSSET  -
   3  * ----------------------------------------------------------------------------
   4  * DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
   5  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
   6  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
   7  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
   8  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
   9  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
  10  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  11  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  12  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  13  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  14  * ----------------------------------------------------------------------------
  15  * File Name           : lib_AT91SAM7XC256.h
  16  * Object              : AT91SAM7XC256 inlined functions
  17  * Generated           : AT91 SW Application Group  11/02/2005 (17:07:35)
  18  *
  19  * CVS Reference       : /lib_dbgu.h/1.1/Thu Aug 25 12:56:22 2005//
  20  * CVS Reference       : /lib_pmc_SAM7X.h/1.4/Tue Aug 30 13:00:36 2005//
  21  * CVS Reference       : /lib_VREG_6085B.h/1.1/Tue Feb  1 16:20:47 2005//
  22  * CVS Reference       : /lib_rstc_6098A.h/1.1/Wed Oct  6 10:39:20 2004//
  23  * CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
  24  * CVS Reference       : /lib_wdtc_6080A.h/1.1/Wed Oct  6 10:38:30 2004//
  25  * CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
  26  * CVS Reference       : /lib_spi2.h/1.2/Tue Aug 23 15:37:28 2005//
  27  * CVS Reference       : /lib_pitc_6079A.h/1.2/Tue Nov  9 14:43:56 2004//
  28  * CVS Reference       : /lib_aic_6075b.h/1.2/Thu Jul  7 07:48:22 2005//
  29  * CVS Reference       : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//
  30  * CVS Reference       : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
  31  * CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
  32  * CVS Reference       : /lib_rttc_6081A.h/1.1/Wed Oct  6 10:39:38 2004//
  33  * CVS Reference       : /lib_udp.h/1.5/Tue Aug 30 12:13:47 2005//
  34  * CVS Reference       : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//
  35  * CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
  36  * CVS Reference       : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
  37  * CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
  38  * CVS Reference       : /lib_can_AT91.h/1.5/Tue Aug 23 15:37:07 2005//
  39  * CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
  40  * CVS Reference       : /lib_pdc.h/1.2/Tue Jul  2 13:29:40 2002//
  41  * ----------------------------------------------------------------------------
  42  */
  43
  44 #ifndef lib_AT91SAM7XC256_H
  45 #define lib_AT91SAM7XC256_H
  46
  47 /**
  48  * \addtogroup board
  49  * @{
  50  */
  51
  52 /**
  53  * @file
  54  * @brief Microcontroller AT91SAM7XC256 inline function library.
  55  *
  56  * M2M changes:
  57  * \date 20071017 PWZ Changed AT91F_EMAC_CfgPIO
  58  * \date 20071025 PWZ Changed comment in AT91F_EMAC_CfgPIO for AT91C_PB18_EF100 (don't use).
  59  * \date 20080212 PWZ Changed preprocessor if-else in AT91F_EMAC_CfgPIO. Only EK board includes extra code.
  60  * \date 20081128 PWZ Changed config_define_board values.
  61  *
  62  */
  63
  64
  65 #include "AT91SAM7XC256.h"
  66
  67 /* M2M */
  68 // #include "m2m_Config.h"
  69
  70
  71 /* M2M
  72  * Remove (temporarily) this define when using the MISRA-checker.
  73  * org: #define __inline static inline
  74  */
  75 #define __inline static __attribute__((unused))
  76
  77 /******************************************************************************
  78  *              SOFTWARE API FOR AIC
  79  ******************************************************************************/
  80 #define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
  81
  82
  83 //*----------------------------------------------------------------------------
  84 //* \fn    AT91F_AIC_ConfigureIt
  85 //* \brief Interrupt Handler Initialization
  86 //*----------------------------------------------------------------------------
  87 __inline unsigned int AT91F_AIC_ConfigureIt (
  88         AT91PS_AIC pAic,  // \arg pointer to the AIC registers
  89         unsigned int irq_id,     // \arg interrupt number to initialize
  90         unsigned int priority,   // \arg priority to give to the interrupt
  91         unsigned int src_type,   // \arg activation and sense of activation
  92         void (*newHandler) () ) // \arg address of the interrupt handler
  93 {
  94         unsigned int oldHandler;
  95     unsigned int mask ;
  96
  97     oldHandler = pAic->AIC_SVR[irq_id];
  98
  99     mask = 0x1 << irq_id ;
 100     //* Disable the interrupt on the interrupt controller
 101     pAic->AIC_IDCR = mask ;
 102     //* Save the interrupt handler routine pointer and the interrupt priority
 103     pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
 104     //* Store the Source Mode Register
 105     pAic->AIC_SMR[irq_id] = src_type | priority  ;
 106     //* Clear the interrupt on the interrupt controller
 107     pAic->AIC_ICCR = mask ;
 108
 109         return oldHandler;
 110 }
 111
 112 //*----------------------------------------------------------------------------
 113 //* \fn    AT91F_AIC_EnableIt
 114 //* \brief Enable corresponding IT number
 115 //*----------------------------------------------------------------------------
 116 __inline void AT91F_AIC_EnableIt (
 117         AT91PS_AIC pAic,      // \arg pointer to the AIC registers
 118         unsigned int irq_id ) // \arg interrupt number to initialize
 119 {
 120     //* Enable the interrupt on the interrupt controller
 121     pAic->AIC_IECR = 0x1 << irq_id ;
 122 }
 123
 124 //*----------------------------------------------------------------------------
 125 //* \fn    AT91F_AIC_DisableIt
 126 //* \brief Disable corresponding IT number
 127 //*----------------------------------------------------------------------------
 128 __inline void AT91F_AIC_DisableIt (
 129         AT91PS_AIC pAic,      // \arg pointer to the AIC registers
 130         unsigned int irq_id ) // \arg interrupt number to initialize
 131 {
 132     unsigned int mask = 0x1 << irq_id;
 133     //* Disable the interrupt on the interrupt controller
 134     pAic->AIC_IDCR = mask ;
 135     //* Clear the interrupt on the Interrupt Controller ( if one is pending )
 136     pAic->AIC_ICCR = mask ;
 137 }
 138
 139 //*----------------------------------------------------------------------------
 140 //* \fn    AT91F_AIC_ClearIt
 141 //* \brief Clear corresponding IT number
 142 //*----------------------------------------------------------------------------
 143 __inline void AT91F_AIC_ClearIt (
 144         AT91PS_AIC pAic,     // \arg pointer to the AIC registers
 145         unsigned int irq_id) // \arg interrupt number to initialize
 146 {
 147     //* Clear the interrupt on the Interrupt Controller ( if one is pending )
 148     pAic->AIC_ICCR = (0x1 << irq_id);
 149 }
 150
 151 //*----------------------------------------------------------------------------
 152 //* \fn    AT91F_AIC_AcknowledgeIt
 153 //* \brief Acknowledge corresponding IT number
 154 //*----------------------------------------------------------------------------
 155 __inline void AT91F_AIC_AcknowledgeIt (
 156         AT91PS_AIC pAic)     // \arg pointer to the AIC registers
 157 {
 158     pAic->AIC_EOICR = pAic->AIC_EOICR;
 159 }
 160
 161 //*----------------------------------------------------------------------------
 162 //* \fn    AT91F_AIC_SetExceptionVector
 163 //* \brief Configure vector handler
 164 //*----------------------------------------------------------------------------
 165 __inline unsigned int  AT91F_AIC_SetExceptionVector (
 166         unsigned int *pVector, // \arg pointer to the AIC registers
 167         void (*Handler) () )   // \arg Interrupt Handler
 168 {
 169         unsigned int oldVector = *pVector;
 170
 171         if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
 172                 *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
 173         else
 174                 *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
 175
 176         return oldVector;
 177 }
 178
 179 //*----------------------------------------------------------------------------
 180 //* \fn    AT91F_AIC_Trig
 181 //* \brief Trig an IT
 182 //*----------------------------------------------------------------------------
 183 __inline void  AT91F_AIC_Trig (
 184         AT91PS_AIC pAic,     // \arg pointer to the AIC registers
 185         unsigned int irq_id) // \arg interrupt number
 186 {
 187         pAic->AIC_ISCR = (0x1 << irq_id) ;
 188 }
 189
 190 //*----------------------------------------------------------------------------
 191 //* \fn    AT91F_AIC_IsActive
 192 //* \brief Test if an IT is active
 193 //*----------------------------------------------------------------------------
 194 __inline unsigned int  AT91F_AIC_IsActive (
 195         AT91PS_AIC pAic,     // \arg pointer to the AIC registers
 196         unsigned int irq_id) // \arg Interrupt Number
 197 {
 198         return (pAic->AIC_ISR & (0x1 << irq_id));
 199 }
 200
 201 //*----------------------------------------------------------------------------
 202 //* \fn    AT91F_AIC_IsPending
 203 //* \brief Test if an IT is pending
 204 //*----------------------------------------------------------------------------
 205 __inline unsigned int  AT91F_AIC_IsPending (
 206         AT91PS_AIC pAic,     // \arg pointer to the AIC registers
 207         unsigned int irq_id) // \arg Interrupt Number
 208 {
 209         return (pAic->AIC_IPR & (0x1 << irq_id));
 210 }
 211
 212 //*----------------------------------------------------------------------------
 213 //* \fn    AT91F_AIC_Open
 214 //* \brief Set exception vectors and AIC registers to default values
 215 //*----------------------------------------------------------------------------
 216 __inline void AT91F_AIC_Open(
 217         AT91PS_AIC pAic,        // \arg pointer to the AIC registers
 218         void (*IrqHandler) (),  // \arg Default IRQ vector exception
 219         void (*FiqHandler) (),  // \arg Default FIQ vector exception
 220         void (*DefaultHandler)  (), // \arg Default Handler set in ISR
 221         void (*SpuriousHandler) (), // \arg Default Spurious Handler
 222         unsigned int protectMode)   // \arg Debug Control Register
 223 {
 224         int i;
 225
 226         // Disable all interrupts and set IVR to the default handler
 227         for (i = 0; i < 32; ++i) {
 228                 AT91F_AIC_DisableIt(pAic, i);
 229                 AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler);
 230         }
 231
 232         // Set the IRQ exception vector
 233         AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
 234         // Set the Fast Interrupt exception vector
 235         AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
 236
 237         pAic->AIC_SPU = (unsigned int) SpuriousHandler;
 238         pAic->AIC_DCR = protectMode;
 239 }
 240 /* *****************************************************************************
 241                 SOFTWARE API FOR PDC
 242    ***************************************************************************** */
 243 //*----------------------------------------------------------------------------
 244 //* \fn    AT91F_PDC_SetNextRx
 245 //* \brief Set the next receive transfer descriptor
 246 //*----------------------------------------------------------------------------
 247 __inline void AT91F_PDC_SetNextRx (
 248         AT91PS_PDC pPDC,     // \arg pointer to a PDC controller
 249         char *address,       // \arg address to the next bloc to be received
 250         unsigned int bytes)  // \arg number of bytes to be received
 251 {
 252         pPDC->PDC_RNPR = (unsigned int) address;
 253         pPDC->PDC_RNCR = bytes;
 254 }
 255
 256 //*----------------------------------------------------------------------------
 257 //* \fn    AT91F_PDC_SetNextTx
 258 //* \brief Set the next transmit transfer descriptor
 259 //*----------------------------------------------------------------------------
 260 __inline void AT91F_PDC_SetNextTx (
 261         AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
 262         char *address,         // \arg address to the next bloc to be transmitted
 263         unsigned int bytes)    // \arg number of bytes to be transmitted
 264 {
 265         pPDC->PDC_TNPR = (unsigned int) address;
 266         pPDC->PDC_TNCR = bytes;
 267 }
 268
 269 //*----------------------------------------------------------------------------
 270 //* \fn    AT91F_PDC_SetRx
 271 //* \brief Set the receive transfer descriptor
 272 //*----------------------------------------------------------------------------
 273 __inline void AT91F_PDC_SetRx (
 274         AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
 275         char *address,         // \arg address to the next bloc to be received
 276         unsigned int bytes)    // \arg number of bytes to be received
 277 {
 278         pPDC->PDC_RPR = (unsigned int) address;
 279         pPDC->PDC_RCR = bytes;
 280 }
 281
 282 //*----------------------------------------------------------------------------
 283 //* \fn    AT91F_PDC_SetTx
 284 //* \brief Set the transmit transfer descriptor
 285 //*----------------------------------------------------------------------------
 286 __inline void AT91F_PDC_SetTx (
 287         AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
 288         char *address,         // \arg address to the next bloc to be transmitted
 289         unsigned int bytes)    // \arg number of bytes to be transmitted
 290 {
 291         pPDC->PDC_TPR = (unsigned int) address;
 292         pPDC->PDC_TCR = bytes;
 293 }
 294
 295 //*----------------------------------------------------------------------------
 296 //* \fn    AT91F_PDC_EnableTx
 297 //* \brief Enable transmit
 298 //*----------------------------------------------------------------------------
 299 __inline void AT91F_PDC_EnableTx (
 300         AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
 301 {
 302         pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
 303 }
 304
 305 //*----------------------------------------------------------------------------
 306 //* \fn    AT91F_PDC_EnableRx
 307 //* \brief Enable receive
 308 //*----------------------------------------------------------------------------
 309 __inline void AT91F_PDC_EnableRx (
 310         AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
 311 {
 312         pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
 313 }
 314
 315 //*----------------------------------------------------------------------------
 316 //* \fn    AT91F_PDC_DisableTx
 317 //* \brief Disable transmit
 318 //*----------------------------------------------------------------------------
 319 __inline void AT91F_PDC_DisableTx (
 320         AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
 321 {
 322         pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
 323 }
 324
 325 //*----------------------------------------------------------------------------
 326 //* \fn    AT91F_PDC_DisableRx
 327 //* \brief Disable receive
 328 //*----------------------------------------------------------------------------
 329 __inline void AT91F_PDC_DisableRx (
 330         AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
 331 {
 332         pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
 333 }
 334
 335 //*----------------------------------------------------------------------------
 336 //* \fn    AT91F_PDC_IsTxEmpty
 337 //* \brief Test if the current transfer descriptor has been sent
 338 //*----------------------------------------------------------------------------
 339 __inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
 340         AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
 341 {
 342         return !(pPDC->PDC_TCR);
 343 }
 344
 345 //*----------------------------------------------------------------------------
 346 //* \fn    AT91F_PDC_IsNextTxEmpty
 347 //* \brief Test if the next transfer descriptor has been moved to the current td
 348 //*----------------------------------------------------------------------------
 349 __inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
 350         AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
 351 {
 352         return !(pPDC->PDC_TNCR);
 353 }
 354
 355 //*----------------------------------------------------------------------------
 356 //* \fn    AT91F_PDC_IsRxEmpty
 357 //* \brief Test if the current transfer descriptor has been filled
 358 //*----------------------------------------------------------------------------
 359 __inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
 360         AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
 361 {
 362         return !(pPDC->PDC_RCR);
 363 }
 364
 365 //*----------------------------------------------------------------------------
 366 //* \fn    AT91F_PDC_IsNextRxEmpty
 367 //* \brief Test if the next transfer descriptor has been moved to the current td
 368 //*----------------------------------------------------------------------------
 369 __inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
 370         AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
 371 {
 372         return !(pPDC->PDC_RNCR);
 373 }
 374
 375 //*----------------------------------------------------------------------------
 376 //* \fn    AT91F_PDC_Open
 377 //* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
 378 //*----------------------------------------------------------------------------
 379 __inline void AT91F_PDC_Open (
 380         AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
 381 {
 382     //* Disable the RX and TX PDC transfer requests
 383         AT91F_PDC_DisableRx(pPDC);
 384         AT91F_PDC_DisableTx(pPDC);
 385
 386         //* Reset all Counter register Next buffer first
 387         AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
 388         AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
 389         AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
 390         AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
 391
 392     //* Enable the RX and TX PDC transfer requests
 393         AT91F_PDC_EnableRx(pPDC);
 394         AT91F_PDC_EnableTx(pPDC);
 395 }
 396
 397 //*----------------------------------------------------------------------------
 398 //* \fn    AT91F_PDC_Close
 399 //* \brief Close PDC: disable TX and RX reset transfer descriptors
 400 //*----------------------------------------------------------------------------
 401 __inline void AT91F_PDC_Close (
 402         AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
 403 {
 404     //* Disable the RX and TX PDC transfer requests
 405         AT91F_PDC_DisableRx(pPDC);
 406         AT91F_PDC_DisableTx(pPDC);
 407
 408         //* Reset all Counter register Next buffer first
 409         AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
 410         AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
 411         AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
 412         AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
 413
 414 }
 415
 416 //*----------------------------------------------------------------------------
 417 //* \fn    AT91F_PDC_SendFrame
 418 //* \brief Close PDC: disable TX and RX reset transfer descriptors
 419 //*----------------------------------------------------------------------------
 420 __inline unsigned int AT91F_PDC_SendFrame(
 421         AT91PS_PDC pPDC,
 422         char *pBuffer,
 423         unsigned int szBuffer,
 424         char *pNextBuffer,
 425         unsigned int szNextBuffer )
 426 {
 427         if (AT91F_PDC_IsTxEmpty(pPDC)) {
 428                 //* Buffer and next buffer can be initialized
 429                 AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
 430                 AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
 431                 return 2;
 432         }
 433         else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
 434                 //* Only one buffer can be initialized
 435                 AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
 436                 return 1;
 437         }
 438         else {
 439                 //* All buffer are in use...
 440                 return 0;
 441         }
 442 }
 443
 444 //*----------------------------------------------------------------------------
 445 //* \fn    AT91F_PDC_ReceiveFrame
 446 //* \brief Close PDC: disable TX and RX reset transfer descriptors
 447 //*----------------------------------------------------------------------------
 448 __inline unsigned int AT91F_PDC_ReceiveFrame (
 449         AT91PS_PDC pPDC,
 450         char *pBuffer,
 451         unsigned int szBuffer,
 452         char *pNextBuffer,
 453         unsigned int szNextBuffer )
 454 {
 455         if (AT91F_PDC_IsRxEmpty(pPDC)) {
 456                 //* Buffer and next buffer can be initialized
 457                 AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
 458                 AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
 459                 return 2;
 460         }
 461         else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
 462                 //* Only one buffer can be initialized
 463                 AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
 464                 return 1;
 465         }
 466         else {
 467                 //* All buffer are in use...
 468                 return 0;
 469         }
 470 }
 471 /* *****************************************************************************
 472                 SOFTWARE API FOR DBGU
 473    ***************************************************************************** */
 474 //*----------------------------------------------------------------------------
 475 //* \fn    AT91F_DBGU_InterruptEnable
 476 //* \brief Enable DBGU Interrupt
 477 //*----------------------------------------------------------------------------
 478 __inline void AT91F_DBGU_InterruptEnable(
 479         AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
 480         unsigned int flag) // \arg  dbgu interrupt to be enabled
 481 {
 482         pDbgu->DBGU_IER = flag;
 483 }
 484
 485 //*----------------------------------------------------------------------------
 486 //* \fn    AT91F_DBGU_InterruptDisable
 487 //* \brief Disable DBGU Interrupt
 488 //*----------------------------------------------------------------------------
 489 __inline void AT91F_DBGU_InterruptDisable(
 490         AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
 491         unsigned int flag) // \arg  dbgu interrupt to be disabled
 492 {
 493         pDbgu->DBGU_IDR = flag;
 494 }
 495
 496 //*----------------------------------------------------------------------------
 497 //* \fn    AT91F_DBGU_GetInterruptMaskStatus
 498 //* \brief Return DBGU Interrupt Mask Status
 499 //*----------------------------------------------------------------------------
 500 __inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
 501         AT91PS_DBGU pDbgu) // \arg  pointer to a DBGU controller
 502 {
 503         return pDbgu->DBGU_IMR;
 504 }
 505
 506 //*----------------------------------------------------------------------------
 507 //* \fn    AT91F_DBGU_IsInterruptMasked
 508 //* \brief Test if DBGU Interrupt is Masked
 509 //*----------------------------------------------------------------------------
 510 __inline int AT91F_DBGU_IsInterruptMasked(
 511         AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
 512         unsigned int flag) // \arg  flag to be tested
 513 {
 514         return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
 515 }
 516
 517 /* *****************************************************************************
 518                 SOFTWARE API FOR PIO
 519    ***************************************************************************** */
 520 //*----------------------------------------------------------------------------
 521 //* \fn    AT91F_PIO_CfgPeriph
 522 //* \brief Enable pins to be drived by peripheral
 523 //*----------------------------------------------------------------------------
 524 __inline void AT91F_PIO_CfgPeriph(
 525         AT91PS_PIO pPio,             // \arg pointer to a PIO controller
 526         unsigned int periphAEnable,  // \arg PERIPH A to enable
 527         unsigned int periphBEnable)  // \arg PERIPH B to enable
 528
 529 {
 530         pPio->PIO_ASR = periphAEnable;
 531         pPio->PIO_BSR = periphBEnable;
 532         pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
 533 }
 534
 535 //*----------------------------------------------------------------------------
 536 //* \fn    AT91F_PIO_CfgOutput
 537 //* \brief Enable PIO in output mode
 538 //*----------------------------------------------------------------------------
 539 __inline void AT91F_PIO_CfgOutput(
 540         AT91PS_PIO pPio,             // \arg pointer to a PIO controller
 541         unsigned int pioEnable)      // \arg PIO to be enabled
 542 {
 543         pPio->PIO_PER = pioEnable; // Set in PIO mode
 544         pPio->PIO_OER = pioEnable; // Configure in Output
 545 }
 546
 547 //*----------------------------------------------------------------------------
 548 //* \fn    AT91F_PIO_CfgInput
 549 //* \brief Enable PIO in input mode
 550 //*----------------------------------------------------------------------------
 551 __inline void AT91F_PIO_CfgInput(
 552         AT91PS_PIO pPio,             // \arg pointer to a PIO controller
 553         unsigned int inputEnable)      // \arg PIO to be enabled
 554 {
 555         // Disable output
 556         pPio->PIO_ODR  = inputEnable;
 557         pPio->PIO_PER  = inputEnable;
 558 }
 559
 560 //*----------------------------------------------------------------------------
 561 //* \fn    AT91F_PIO_CfgOpendrain
 562 //* \brief Configure PIO in open drain
 563 //*----------------------------------------------------------------------------
 564 __inline void AT91F_PIO_CfgOpendrain(
 565         AT91PS_PIO pPio,             // \arg pointer to a PIO controller
 566         unsigned int multiDrvEnable) // \arg pio to be configured in open drain
 567 {
 568         // Configure the multi-drive option
 569         pPio->PIO_MDDR = ~multiDrvEnable;
 570         pPio->PIO_MDER = multiDrvEnable;
 571 }
 572
 573 //*----------------------------------------------------------------------------
 574 //* \fn    AT91F_PIO_CfgPullup
 575 //* \brief Enable pullup on PIO
 576 //*----------------------------------------------------------------------------
 577 __inline void AT91F_PIO_CfgPullup(
 578         AT91PS_PIO pPio,             // \arg pointer to a PIO controller
 579         unsigned int pullupEnable)   // \arg enable pullup on PIO
 580 {
 581                 // Connect or not Pullup
 582         pPio->PIO_PPUDR = ~pullupEnable;
 583         pPio->PIO_PPUER = pullupEnable;
 584 }
 585
 586 //*----------------------------------------------------------------------------
 587 //* \fn    AT91F_PIO_CfgDirectDrive
 588 //* \brief Enable direct drive on PIO
 589 //*----------------------------------------------------------------------------
 590 __inline void AT91F_PIO_CfgDirectDrive(
 591         AT91PS_PIO pPio,             // \arg pointer to a PIO controller
 592         unsigned int directDrive)    // \arg PIO to be configured with direct drive
 593
 594 {
 595         // Configure the Direct Drive
 596         pPio->PIO_OWDR  = ~directDrive;
 597         pPio->PIO_OWER  = directDrive;
 598 }
 599
 600 //*----------------------------------------------------------------------------
 601 //* \fn    AT91F_PIO_CfgInputFilter
 602 //* \brief Enable input filter on input PIO
 603 //*----------------------------------------------------------------------------
 604 __inline void AT91F_PIO_CfgInputFilter(
 605         AT91PS_PIO pPio,             // \arg pointer to a PIO controller
 606         unsigned int inputFilter)    // \arg PIO to be configured with input filter
 607
 608 {
 609         // Configure the Direct Drive
 610         pPio->PIO_IFDR  = ~inputFilter;
 611         pPio->PIO_IFER  = inputFilter;
 612 }
 613
 614 //*----------------------------------------------------------------------------
 615 //* \fn    AT91F_PIO_GetInput
 616 //* \brief Return PIO input value
 617 //*----------------------------------------------------------------------------
 618 __inline unsigned int AT91F_PIO_GetInput( // \return PIO input
 619         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
 620 {
 621         return pPio->PIO_PDSR;
 622 }
 623
 624 //*----------------------------------------------------------------------------
 625 //* \fn    AT91F_PIO_IsInputSet
 626 //* \brief Test if PIO is input flag is active
 627 //*----------------------------------------------------------------------------
 628 __inline int AT91F_PIO_IsInputSet(
 629         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 630         unsigned int flag) // \arg  flag to be tested
 631 {
 632         return (AT91F_PIO_GetInput(pPio) & flag);
 633 }
 634
 635
 636 //*----------------------------------------------------------------------------
 637 //* \fn    AT91F_PIO_SetOutput
 638 //* \brief Set to 1 output PIO
 639 //*----------------------------------------------------------------------------
 640 __inline void AT91F_PIO_SetOutput(
 641         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 642         unsigned int flag) // \arg  output to be set
 643 {
 644         pPio->PIO_SODR = flag;
 645 }
 646
 647 //*----------------------------------------------------------------------------
 648 //* \fn    AT91F_PIO_ClearOutput
 649 //* \brief Set to 0 output PIO
 650 //*----------------------------------------------------------------------------
 651 __inline void AT91F_PIO_ClearOutput(
 652         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 653         unsigned int flag) // \arg  output to be cleared
 654 {
 655         pPio->PIO_CODR = flag;
 656 }
 657
 658 //*----------------------------------------------------------------------------
 659 //* \fn    AT91F_PIO_ForceOutput
 660 //* \brief Force output when Direct drive option is enabled
 661 //*----------------------------------------------------------------------------
 662 __inline void AT91F_PIO_ForceOutput(
 663         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 664         unsigned int flag) // \arg  output to be forced
 665 {
 666         pPio->PIO_ODSR = flag;
 667 }
 668
 669 //*----------------------------------------------------------------------------
 670 //* \fn    AT91F_PIO_Enable
 671 //* \brief Enable PIO
 672 //*----------------------------------------------------------------------------
 673 __inline void AT91F_PIO_Enable(
 674         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 675         unsigned int flag) // \arg  pio to be enabled
 676 {
 677         pPio->PIO_PER = flag;
 678 }
 679
 680 //*----------------------------------------------------------------------------
 681 //* \fn    AT91F_PIO_Disable
 682 //* \brief Disable PIO
 683 //*----------------------------------------------------------------------------
 684 __inline void AT91F_PIO_Disable(
 685         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 686         unsigned int flag) // \arg  pio to be disabled
 687 {
 688         pPio->PIO_PDR = flag;
 689 }
 690
 691 //*----------------------------------------------------------------------------
 692 //* \fn    AT91F_PIO_GetStatus
 693 //* \brief Return PIO Status
 694 //*----------------------------------------------------------------------------
 695 __inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
 696         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
 697 {
 698         return pPio->PIO_PSR;
 699 }
 700
 701 //*----------------------------------------------------------------------------
 702 //* \fn    AT91F_PIO_IsSet
 703 //* \brief Test if PIO is Set
 704 //*----------------------------------------------------------------------------
 705 __inline int AT91F_PIO_IsSet(
 706         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 707         unsigned int flag) // \arg  flag to be tested
 708 {
 709         return (AT91F_PIO_GetStatus(pPio) & flag);
 710 }
 711
 712 //*----------------------------------------------------------------------------
 713 //* \fn    AT91F_PIO_OutputEnable
 714 //* \brief Output Enable PIO
 715 //*----------------------------------------------------------------------------
 716 __inline void AT91F_PIO_OutputEnable(
 717         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 718         unsigned int flag) // \arg  pio output to be enabled
 719 {
 720         pPio->PIO_OER = flag;
 721 }
 722
 723 //*----------------------------------------------------------------------------
 724 //* \fn    AT91F_PIO_OutputDisable
 725 //* \brief Output Enable PIO
 726 //*----------------------------------------------------------------------------
 727 __inline void AT91F_PIO_OutputDisable(
 728         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 729         unsigned int flag) // \arg  pio output to be disabled
 730 {
 731         pPio->PIO_ODR = flag;
 732 }
 733
 734 //*----------------------------------------------------------------------------
 735 //* \fn    AT91F_PIO_GetOutputStatus
 736 //* \brief Return PIO Output Status
 737 //*----------------------------------------------------------------------------
 738 __inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
 739         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
 740 {
 741         return pPio->PIO_OSR;
 742 }
 743
 744 //*----------------------------------------------------------------------------
 745 //* \fn    AT91F_PIO_IsOuputSet
 746 //* \brief Test if PIO Output is Set
 747 //*----------------------------------------------------------------------------
 748 __inline int AT91F_PIO_IsOutputSet(
 749         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 750         unsigned int flag) // \arg  flag to be tested
 751 {
 752         return (AT91F_PIO_GetOutputStatus(pPio) & flag);
 753 }
 754
 755 //*----------------------------------------------------------------------------
 756 //* \fn    AT91F_PIO_InputFilterEnable
 757 //* \brief Input Filter Enable PIO
 758 //*----------------------------------------------------------------------------
 759 __inline void AT91F_PIO_InputFilterEnable(
 760         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 761         unsigned int flag) // \arg  pio input filter to be enabled
 762 {
 763         pPio->PIO_IFER = flag;
 764 }
 765
 766 //*----------------------------------------------------------------------------
 767 //* \fn    AT91F_PIO_InputFilterDisable
 768 //* \brief Input Filter Disable PIO
 769 //*----------------------------------------------------------------------------
 770 __inline void AT91F_PIO_InputFilterDisable(
 771         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 772         unsigned int flag) // \arg  pio input filter to be disabled
 773 {
 774         pPio->PIO_IFDR = flag;
 775 }
 776
 777 //*----------------------------------------------------------------------------
 778 //* \fn    AT91F_PIO_GetInputFilterStatus
 779 //* \brief Return PIO Input Filter Status
 780 //*----------------------------------------------------------------------------
 781 __inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
 782         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
 783 {
 784         return pPio->PIO_IFSR;
 785 }
 786
 787 //*----------------------------------------------------------------------------
 788 //* \fn    AT91F_PIO_IsInputFilterSet
 789 //* \brief Test if PIO Input filter is Set
 790 //*----------------------------------------------------------------------------
 791 __inline int AT91F_PIO_IsInputFilterSet(
 792         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 793         unsigned int flag) // \arg  flag to be tested
 794 {
 795         return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
 796 }
 797
 798 //*----------------------------------------------------------------------------
 799 //* \fn    AT91F_PIO_GetOutputDataStatus
 800 //* \brief Return PIO Output Data Status
 801 //*----------------------------------------------------------------------------
 802 __inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status
 803         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
 804 {
 805         return pPio->PIO_ODSR;
 806 }
 807
 808 //*----------------------------------------------------------------------------
 809 //* \fn    AT91F_PIO_InterruptEnable
 810 //* \brief Enable PIO Interrupt
 811 //*----------------------------------------------------------------------------
 812 __inline void AT91F_PIO_InterruptEnable(
 813         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 814         unsigned int flag) // \arg  pio interrupt to be enabled
 815 {
 816         pPio->PIO_IER = flag;
 817 }
 818
 819 //*----------------------------------------------------------------------------
 820 //* \fn    AT91F_PIO_InterruptDisable
 821 //* \brief Disable PIO Interrupt
 822 //*----------------------------------------------------------------------------
 823 __inline void AT91F_PIO_InterruptDisable(
 824         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 825         unsigned int flag) // \arg  pio interrupt to be disabled
 826 {
 827         pPio->PIO_IDR = flag;
 828 }
 829
 830 //*----------------------------------------------------------------------------
 831 //* \fn    AT91F_PIO_GetInterruptMaskStatus
 832 //* \brief Return PIO Interrupt Mask Status
 833 //*----------------------------------------------------------------------------
 834 __inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
 835         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
 836 {
 837         return pPio->PIO_IMR;
 838 }
 839
 840 //*----------------------------------------------------------------------------
 841 //* \fn    AT91F_PIO_GetInterruptStatus
 842 //* \brief Return PIO Interrupt Status
 843 //*----------------------------------------------------------------------------
 844 __inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
 845         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
 846 {
 847         return pPio->PIO_ISR;
 848 }
 849
 850 //*----------------------------------------------------------------------------
 851 //* \fn    AT91F_PIO_IsInterruptMasked
 852 //* \brief Test if PIO Interrupt is Masked
 853 //*----------------------------------------------------------------------------
 854 __inline int AT91F_PIO_IsInterruptMasked(
 855         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 856         unsigned int flag) // \arg  flag to be tested
 857 {
 858         return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
 859 }
 860
 861 //*----------------------------------------------------------------------------
 862 //* \fn    AT91F_PIO_IsInterruptSet
 863 //* \brief Test if PIO Interrupt is Set
 864 //*----------------------------------------------------------------------------
 865 __inline int AT91F_PIO_IsInterruptSet(
 866         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 867         unsigned int flag) // \arg  flag to be tested
 868 {
 869         return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
 870 }
 871
 872 //*----------------------------------------------------------------------------
 873 //* \fn    AT91F_PIO_MultiDriverEnable
 874 //* \brief Multi Driver Enable PIO
 875 //*----------------------------------------------------------------------------
 876 __inline void AT91F_PIO_MultiDriverEnable(
 877         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 878         unsigned int flag) // \arg  pio to be enabled
 879 {
 880         pPio->PIO_MDER = flag;
 881 }
 882
 883 //*----------------------------------------------------------------------------
 884 //* \fn    AT91F_PIO_MultiDriverDisable
 885 //* \brief Multi Driver Disable PIO
 886 //*----------------------------------------------------------------------------
 887 __inline void AT91F_PIO_MultiDriverDisable(
 888         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 889         unsigned int flag) // \arg  pio to be disabled
 890 {
 891         pPio->PIO_MDDR = flag;
 892 }
 893
 894 //*----------------------------------------------------------------------------
 895 //* \fn    AT91F_PIO_GetMultiDriverStatus
 896 //* \brief Return PIO Multi Driver Status
 897 //*----------------------------------------------------------------------------
 898 __inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
 899         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
 900 {
 901         return pPio->PIO_MDSR;
 902 }
 903
 904 //*----------------------------------------------------------------------------
 905 //* \fn    AT91F_PIO_IsMultiDriverSet
 906 //* \brief Test if PIO MultiDriver is Set
 907 //*----------------------------------------------------------------------------
 908 __inline int AT91F_PIO_IsMultiDriverSet(
 909         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 910         unsigned int flag) // \arg  flag to be tested
 911 {
 912         return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
 913 }
 914
 915 //*----------------------------------------------------------------------------
 916 //* \fn    AT91F_PIO_A_RegisterSelection
 917 //* \brief PIO A Register Selection
 918 //*----------------------------------------------------------------------------
 919 __inline void AT91F_PIO_A_RegisterSelection(
 920         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 921         unsigned int flag) // \arg  pio A register selection
 922 {
 923         pPio->PIO_ASR = flag;
 924 }
 925
 926 //*----------------------------------------------------------------------------
 927 //* \fn    AT91F_PIO_B_RegisterSelection
 928 //* \brief PIO B Register Selection
 929 //*----------------------------------------------------------------------------
 930 __inline void AT91F_PIO_B_RegisterSelection(
 931         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 932         unsigned int flag) // \arg  pio B register selection
 933 {
 934         pPio->PIO_BSR = flag;
 935 }
 936
 937 //*----------------------------------------------------------------------------
 938 //* \fn    AT91F_PIO_Get_AB_RegisterStatus
 939 //* \brief Return PIO Interrupt Status
 940 //*----------------------------------------------------------------------------
 941 __inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
 942         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
 943 {
 944         return pPio->PIO_ABSR;
 945 }
 946
 947 //*----------------------------------------------------------------------------
 948 //* \fn    AT91F_PIO_IsAB_RegisterSet
 949 //* \brief Test if PIO AB Register is Set
 950 //*----------------------------------------------------------------------------
 951 __inline int AT91F_PIO_IsAB_RegisterSet(
 952         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 953         unsigned int flag) // \arg  flag to be tested
 954 {
 955         return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
 956 }
 957
 958 //*----------------------------------------------------------------------------
 959 //* \fn    AT91F_PIO_OutputWriteEnable
 960 //* \brief Output Write Enable PIO
 961 //*----------------------------------------------------------------------------
 962 __inline void AT91F_PIO_OutputWriteEnable(
 963         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 964         unsigned int flag) // \arg  pio output write to be enabled
 965 {
 966         pPio->PIO_OWER = flag;
 967 }
 968
 969 //*----------------------------------------------------------------------------
 970 //* \fn    AT91F_PIO_OutputWriteDisable
 971 //* \brief Output Write Disable PIO
 972 //*----------------------------------------------------------------------------
 973 __inline void AT91F_PIO_OutputWriteDisable(
 974         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 975         unsigned int flag) // \arg  pio output write to be disabled
 976 {
 977         pPio->PIO_OWDR = flag;
 978 }
 979
 980 //*----------------------------------------------------------------------------
 981 //* \fn    AT91F_PIO_GetOutputWriteStatus
 982 //* \brief Return PIO Output Write Status
 983 //*----------------------------------------------------------------------------
 984 __inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
 985         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
 986 {
 987         return pPio->PIO_OWSR;
 988 }
 989
 990 //*----------------------------------------------------------------------------
 991 //* \fn    AT91F_PIO_IsOutputWriteSet
 992 //* \brief Test if PIO OutputWrite is Set
 993 //*----------------------------------------------------------------------------
 994 __inline int AT91F_PIO_IsOutputWriteSet(
 995         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
 996         unsigned int flag) // \arg  flag to be tested
 997 {
 998         return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
 999 }
1000
1001 //*----------------------------------------------------------------------------
1002 //* \fn    AT91F_PIO_GetCfgPullup
1003 //* \brief Return PIO Configuration Pullup
1004 //*----------------------------------------------------------------------------
1005 __inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup
1006         AT91PS_PIO pPio) // \arg  pointer to a PIO controller
1007 {
1008         return pPio->PIO_PPUSR;
1009 }
1010
1011 //*----------------------------------------------------------------------------
1012 //* \fn    AT91F_PIO_IsOutputDataStatusSet
1013 //* \brief Test if PIO Output Data Status is Set
1014 //*----------------------------------------------------------------------------
1015 __inline int AT91F_PIO_IsOutputDataStatusSet(
1016         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1017         unsigned int flag) // \arg  flag to be tested
1018 {
1019         return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
1020 }
1021
1022 //*----------------------------------------------------------------------------
1023 //* \fn    AT91F_PIO_IsCfgPullupStatusSet
1024 //* \brief Test if PIO Configuration Pullup Status is Set
1025 //*----------------------------------------------------------------------------
1026 __inline int AT91F_PIO_IsCfgPullupStatusSet(
1027         AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
1028         unsigned int flag) // \arg  flag to be tested
1029 {
1030         return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
1031 }
1032
1033 /* *****************************************************************************
1034                 SOFTWARE API FOR PMC
1035    ***************************************************************************** */
1036 //*----------------------------------------------------------------------------
1037 //* \fn    AT91F_PMC_CfgSysClkEnableReg
1038 //* \brief Configure the System Clock Enable Register of the PMC controller
1039 //*----------------------------------------------------------------------------
1040 __inline void AT91F_PMC_CfgSysClkEnableReg (
1041         AT91PS_PMC pPMC, // \arg pointer to PMC controller
1042         unsigned int mode)
1043 {
1044         //* Write to the SCER register
1045         pPMC->PMC_SCER = mode;
1046 }
1047
1048 //*----------------------------------------------------------------------------
1049 //* \fn    AT91F_PMC_CfgSysClkDisableReg
1050 //* \brief Configure the System Clock Disable Register of the PMC controller
1051 //*----------------------------------------------------------------------------
1052 __inline void AT91F_PMC_CfgSysClkDisableReg (
1053         AT91PS_PMC pPMC, // \arg pointer to PMC controller
1054         unsigned int mode)
1055 {
1056         //* Write to the SCDR register
1057         pPMC->PMC_SCDR = mode;
1058 }
1059
1060 //*----------------------------------------------------------------------------
1061 //* \fn    AT91F_PMC_GetSysClkStatusReg
1062 //* \brief Return the System Clock Status Register of the PMC controller
1063 //*----------------------------------------------------------------------------
1064 __inline unsigned int AT91F_PMC_GetSysClkStatusReg (
1065         AT91PS_PMC pPMC // pointer to a CAN controller
1066         )
1067 {
1068         return pPMC->PMC_SCSR;
1069 }
1070
1071 //*----------------------------------------------------------------------------
1072 //* \fn    AT91F_PMC_EnablePeriphClock
1073 //* \brief Enable peripheral clock
1074 //*----------------------------------------------------------------------------
1075 __inline void AT91F_PMC_EnablePeriphClock (
1076         AT91PS_PMC pPMC, // \arg pointer to PMC controller
1077         unsigned int periphIds)  // \arg IDs of peripherals to enable
1078 {
1079         pPMC->PMC_PCER = periphIds;
1080 }
1081
1082 //*----------------------------------------------------------------------------
1083 //* \fn    AT91F_PMC_DisablePeriphClock
1084 //* \brief Disable peripheral clock
1085 //*----------------------------------------------------------------------------
1086 __inline void AT91F_PMC_DisablePeriphClock (
1087         AT91PS_PMC pPMC, // \arg pointer to PMC controller
1088         unsigned int periphIds)  // \arg IDs of peripherals to enable
1089 {
1090         pPMC->PMC_PCDR = periphIds;
1091 }
1092
1093 //*----------------------------------------------------------------------------
1094 //* \fn    AT91F_PMC_GetPeriphClock
1095 //* \brief Get peripheral clock status
1096 //*----------------------------------------------------------------------------
1097 __inline unsigned int AT91F_PMC_GetPeriphClock (
1098         AT91PS_PMC pPMC) // \arg pointer to PMC controller
1099 {
1100         return pPMC->PMC_PCSR;
1101 }
1102
1103 //*----------------------------------------------------------------------------
1104 //* \fn    AT91F_CKGR_CfgMainOscillatorReg
1105 //* \brief Cfg the main oscillator
1106 //*----------------------------------------------------------------------------
1107 __inline void AT91F_CKGR_CfgMainOscillatorReg (
1108         AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
1109         unsigned int mode)
1110 {
1111         pCKGR->CKGR_MOR = mode;
1112 }
1113
1114 //*----------------------------------------------------------------------------
1115 //* \fn    AT91F_CKGR_GetMainOscillatorReg
1116 //* \brief Cfg the main oscillator
1117 //*----------------------------------------------------------------------------
1118 __inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
1119         AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
1120 {
1121         return pCKGR->CKGR_MOR;
1122 }
1123
1124 //*----------------------------------------------------------------------------
1125 //* \fn    AT91F_CKGR_EnableMainOscillator
1126 //* \brief Enable the main oscillator
1127 //*----------------------------------------------------------------------------
1128 __inline void AT91F_CKGR_EnableMainOscillator(
1129         AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
1130 {
1131         pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
1132 }
1133
1134 //*----------------------------------------------------------------------------
1135 //* \fn    AT91F_CKGR_DisableMainOscillator
1136 //* \brief Disable the main oscillator
1137 //*----------------------------------------------------------------------------
1138 __inline void AT91F_CKGR_DisableMainOscillator (
1139         AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
1140 {
1141         pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
1142 }
1143
1144 //*----------------------------------------------------------------------------
1145 //* \fn    AT91F_CKGR_CfgMainOscStartUpTime
1146 //* \brief Cfg MOR Register according to the main osc startup time
1147 //*----------------------------------------------------------------------------
1148 __inline void AT91F_CKGR_CfgMainOscStartUpTime (
1149         AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
1150         unsigned int startup_time,  // \arg main osc startup time in microsecond (us)
1151         unsigned int slowClock)  // \arg slowClock in Hz
1152 {
1153         pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
1154         pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
1155 }
1156
1157 //*----------------------------------------------------------------------------
1158 //* \fn    AT91F_CKGR_GetMainClockFreqReg
1159 //* \brief Cfg the main oscillator
1160 //*----------------------------------------------------------------------------
1161 __inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
1162         AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
1163 {
1164         return pCKGR->CKGR_MCFR;
1165 }
1166
1167 //*----------------------------------------------------------------------------
1168 //* \fn    AT91F_CKGR_GetMainClock
1169 //* \brief Return Main clock in Hz
1170 //*----------------------------------------------------------------------------
1171 __inline unsigned int AT91F_CKGR_GetMainClock (
1172         AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
1173         unsigned int slowClock)  // \arg slowClock in Hz
1174 {
1175         return ((pCKGR->CKGR_MCFR  & AT91C_CKGR_MAINF) * slowClock) >> 4;
1176 }
1177
1178 //*----------------------------------------------------------------------------
1179 //* \fn    AT91F_PMC_CfgMCKReg
1180 //* \brief Cfg Master Clock Register
1181 //*----------------------------------------------------------------------------
1182 __inline void AT91F_PMC_CfgMCKReg (
1183         AT91PS_PMC pPMC, // \arg pointer to PMC controller
1184         unsigned int mode)
1185 {
1186         pPMC->PMC_MCKR = mode;
1187 }
1188
1189 //*----------------------------------------------------------------------------
1190 //* \fn    AT91F_PMC_GetMCKReg
1191 //* \brief Return Master Clock Register
1192 //*----------------------------------------------------------------------------
1193 __inline unsigned int AT91F_PMC_GetMCKReg(
1194         AT91PS_PMC pPMC) // \arg pointer to PMC controller
1195 {
1196         return pPMC->PMC_MCKR;
1197 }
1198
1199 //*------------------------------------------------------------------------------
1200 //* \fn    AT91F_PMC_GetMasterClock
1201 //* \brief Return master clock in Hz which correponds to processor clock for ARM7
1202 //*------------------------------------------------------------------------------
1203 __inline unsigned int AT91F_PMC_GetMasterClock (
1204         AT91PS_PMC pPMC, // \arg pointer to PMC controller
1205         AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
1206         unsigned int slowClock)  // \arg slowClock in Hz
1207 {
1208         unsigned int reg = pPMC->PMC_MCKR;
1209         unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
1210         unsigned int pllDivider, pllMultiplier;
1211
1212         switch (reg & AT91C_PMC_CSS) {
1213                 case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
1214                         return slowClock / prescaler;
1215                 case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
1216                         return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
1217                 case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
1218                         reg = pCKGR->CKGR_PLLR;
1219                         pllDivider    = (reg  & AT91C_CKGR_DIV);
1220                         pllMultiplier = ((reg  & AT91C_CKGR_MUL) >> 16) + 1;
1221                         return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
1222         }
1223         return 0;
1224 }
1225
1226 //*----------------------------------------------------------------------------
1227 //* \fn    AT91F_PMC_EnablePCK
1228 //* \brief Enable peripheral clock
1229 //*----------------------------------------------------------------------------
1230 __inline void AT91F_PMC_EnablePCK (
1231         AT91PS_PMC pPMC, // \arg pointer to PMC controller
1232         unsigned int pck,  // \arg Peripheral clock identifier 0 .. 7
1233         unsigned int mode)
1234 {
1235         pPMC->PMC_PCKR[pck] = mode;
1236         pPMC->PMC_SCER = (1 << pck) << 8;
1237 }
1238
1239 //*----------------------------------------------------------------------------
1240 //* \fn    AT91F_PMC_DisablePCK
1241 //* \brief Enable peripheral clock
1242 //*----------------------------------------------------------------------------
1243 __inline void AT91F_PMC_DisablePCK (
1244         AT91PS_PMC pPMC, // \arg pointer to PMC controller
1245         unsigned int pck)  // \arg Peripheral clock identifier 0 .. 7
1246 {
1247         pPMC->PMC_SCDR = (1 << pck) << 8;
1248 }
1249
1250 //*----------------------------------------------------------------------------
1251 //* \fn    AT91F_PMC_EnableIt
1252 //* \brief Enable PMC interrupt
1253 //*----------------------------------------------------------------------------
1254 __inline void AT91F_PMC_EnableIt (
1255         AT91PS_PMC pPMC,     // pointer to a PMC controller
1256         unsigned int flag)   // IT to be enabled
1257 {
1258         //* Write to the IER register
1259         pPMC->PMC_IER = flag;
1260 }
1261
1262 //*----------------------------------------------------------------------------
1263 //* \fn    AT91F_PMC_DisableIt
1264 //* \brief Disable PMC interrupt
1265 //*----------------------------------------------------------------------------
1266 __inline void AT91F_PMC_DisableIt (
1267         AT91PS_PMC pPMC, // pointer to a PMC controller
1268         unsigned int flag) // IT to be disabled
1269 {
1270         //* Write to the IDR register
1271         pPMC->PMC_IDR = flag;
1272 }
1273
1274 //*----------------------------------------------------------------------------
1275 //* \fn    AT91F_PMC_GetStatus
1276 //* \brief Return PMC Interrupt Status
1277 //*----------------------------------------------------------------------------
1278 __inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status
1279         AT91PS_PMC pPMC) // pointer to a PMC controller
1280 {
1281         return pPMC->PMC_SR;
1282 }
1283
1284 //*----------------------------------------------------------------------------
1285 //* \fn    AT91F_PMC_GetInterruptMaskStatus
1286 //* \brief Return PMC Interrupt Mask Status
1287 //*----------------------------------------------------------------------------
1288 __inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
1289         AT91PS_PMC pPMC) // pointer to a PMC controller
1290 {
1291         return pPMC->PMC_IMR;
1292 }
1293
1294 //*----------------------------------------------------------------------------
1295 //* \fn    AT91F_PMC_IsInterruptMasked
1296 //* \brief Test if PMC Interrupt is Masked
1297 //*----------------------------------------------------------------------------
1298 __inline unsigned int AT91F_PMC_IsInterruptMasked(
1299         AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
1300         unsigned int flag) // \arg  flag to be tested
1301 {
1302         return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);
1303 }
1304
1305 //*----------------------------------------------------------------------------
1306 //* \fn    AT91F_PMC_IsStatusSet
1307 //* \brief Test if PMC Status is Set
1308 //*----------------------------------------------------------------------------
1309 __inline unsigned int AT91F_PMC_IsStatusSet(
1310         AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
1311         unsigned int flag) // \arg  flag to be tested
1312 {
1313         return (AT91F_PMC_GetStatus(pPMC) & flag);
1314 }
1315
1316 // ----------------------------------------------------------------------------
1317 //  \fn    AT91F_CKGR_CfgPLLReg
1318 //  \brief Cfg the PLL Register
1319 // ----------------------------------------------------------------------------
1320 __inline void AT91F_CKGR_CfgPLLReg (
1321         AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
1322         unsigned int mode)
1323 {
1324         pCKGR->CKGR_PLLR = mode;
1325 }
1326
1327 // ----------------------------------------------------------------------------
1328 //  \fn    AT91F_CKGR_GetPLLReg
1329 //  \brief Get the PLL Register
1330 // ----------------------------------------------------------------------------
1331 __inline unsigned int AT91F_CKGR_GetPLLReg (
1332         AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
1333 {
1334         return pCKGR->CKGR_PLLR;
1335 }
1336
1337
1338 /* *****************************************************************************
1339                 SOFTWARE API FOR RSTC
1340    ***************************************************************************** */
1341 //*----------------------------------------------------------------------------
1342 //* \fn    AT91F_RSTSoftReset
1343 //* \brief Start Software Reset
1344 //*----------------------------------------------------------------------------
1345 __inline void AT91F_RSTSoftReset(
1346         AT91PS_RSTC pRSTC,
1347         unsigned int reset)
1348 {
1349         pRSTC->RSTC_RCR = (0xA5000000 | reset);
1350 }
1351
1352 //*----------------------------------------------------------------------------
1353 //* \fn    AT91F_RSTSetMode
1354 //* \brief Set Reset Mode
1355 //*----------------------------------------------------------------------------
1356 __inline void AT91F_RSTSetMode(
1357         AT91PS_RSTC pRSTC,
1358         unsigned int mode)
1359 {
1360         pRSTC->RSTC_RMR = (0xA5000000 | mode);
1361 }
1362
1363 //*----------------------------------------------------------------------------
1364 //* \fn    AT91F_RSTGetMode
1365 //* \brief Get Reset Mode
1366 //*----------------------------------------------------------------------------
1367 __inline unsigned int AT91F_RSTGetMode(
1368         AT91PS_RSTC pRSTC)
1369 {
1370         return (pRSTC->RSTC_RMR);
1371 }
1372
1373 //*----------------------------------------------------------------------------
1374 //* \fn    AT91F_RSTGetStatus
1375 //* \brief Get Reset Status
1376 //*----------------------------------------------------------------------------
1377 __inline unsigned int AT91F_RSTGetStatus(
1378         AT91PS_RSTC pRSTC)
1379 {
1380         return (pRSTC->RSTC_RSR);
1381 }
1382
1383 //*----------------------------------------------------------------------------
1384 //* \fn    AT91F_RSTIsSoftRstActive
1385 //* \brief Return !=0 if software reset is still not completed
1386 //*----------------------------------------------------------------------------
1387 __inline unsigned int AT91F_RSTIsSoftRstActive(
1388         AT91PS_RSTC pRSTC)
1389 {
1390         return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP);
1391 }
1392 /* *****************************************************************************
1393                 SOFTWARE API FOR RTTC
1394    ***************************************************************************** */
1395 //*--------------------------------------------------------------------------------------
1396 //* \fn     AT91F_SetRTT_TimeBase()
1397 //* \brief  Set the RTT prescaler according to the TimeBase in ms
1398 //*--------------------------------------------------------------------------------------
1399 __inline unsigned int AT91F_RTTSetTimeBase(
1400         AT91PS_RTTC pRTTC,
1401         unsigned int ms)
1402 {
1403         if (ms > 2000)
1404                 return 1;   // AT91C_TIME_OUT_OF_RANGE
1405         pRTTC->RTTC_RTMR &= ~0xFFFF;
1406         pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF);
1407         return 0;
1408 }
1409
1410 //*--------------------------------------------------------------------------------------
1411 //* \fn     AT91F_RTTSetPrescaler()
1412 //* \brief  Set the new prescaler value
1413 //*--------------------------------------------------------------------------------------
1414 __inline unsigned int AT91F_RTTSetPrescaler(
1415         AT91PS_RTTC pRTTC,
1416         unsigned int rtpres)
1417 {
1418         pRTTC->RTTC_RTMR &= ~0xFFFF;
1419         pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF);
1420         return (pRTTC->RTTC_RTMR);
1421 }
1422
1423 //*--------------------------------------------------------------------------------------
1424 //* \fn     AT91F_RTTRestart()
1425 //* \brief  Restart the RTT prescaler
1426 //*--------------------------------------------------------------------------------------
1427 __inline void AT91F_RTTRestart(
1428         AT91PS_RTTC pRTTC)
1429 {
1430         pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;
1431 }
1432
1433
1434 //*--------------------------------------------------------------------------------------
1435 //* \fn     AT91F_RTT_SetAlarmINT()
1436 //* \brief  Enable RTT Alarm Interrupt
1437 //*--------------------------------------------------------------------------------------
1438 __inline void AT91F_RTTSetAlarmINT(
1439         AT91PS_RTTC pRTTC)
1440 {
1441         pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
1442 }
1443
1444 //*--------------------------------------------------------------------------------------
1445 //* \fn     AT91F_RTT_ClearAlarmINT()
1446 //* \brief  Disable RTT Alarm Interrupt
1447 //*--------------------------------------------------------------------------------------
1448 __inline void AT91F_RTTClearAlarmINT(
1449         AT91PS_RTTC pRTTC)
1450 {
1451         pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
1452 }
1453
1454 //*--------------------------------------------------------------------------------------
1455 //* \fn     AT91F_RTT_SetRttIncINT()
1456 //* \brief  Enable RTT INC Interrupt
1457 //*--------------------------------------------------------------------------------------
1458 __inline void AT91F_RTTSetRttIncINT(
1459         AT91PS_RTTC pRTTC)
1460 {
1461         pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
1462 }
1463
1464 //*--------------------------------------------------------------------------------------
1465 //* \fn     AT91F_RTT_ClearRttIncINT()
1466 //* \brief  Disable RTT INC Interrupt
1467 //*--------------------------------------------------------------------------------------
1468 __inline void AT91F_RTTClearRttIncINT(
1469         AT91PS_RTTC pRTTC)
1470 {
1471         pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
1472 }
1473
1474 //*--------------------------------------------------------------------------------------
1475 //* \fn     AT91F_RTT_SetAlarmValue()
1476 //* \brief  Set RTT Alarm Value
1477 //*--------------------------------------------------------------------------------------
1478 __inline void AT91F_RTTSetAlarmValue(
1479         AT91PS_RTTC pRTTC, unsigned int alarm)
1480 {
1481         pRTTC->RTTC_RTAR = alarm;
1482 }
1483
1484 //*--------------------------------------------------------------------------------------
1485 //* \fn     AT91F_RTT_GetAlarmValue()
1486 //* \brief  Get RTT Alarm Value
1487 //*--------------------------------------------------------------------------------------
1488 __inline unsigned int AT91F_RTTGetAlarmValue(
1489         AT91PS_RTTC pRTTC)
1490 {
1491         return(pRTTC->RTTC_RTAR);
1492 }
1493
1494 //*--------------------------------------------------------------------------------------
1495 //* \fn     AT91F_RTTGetStatus()
1496 //* \brief  Read the RTT status
1497 //*--------------------------------------------------------------------------------------
1498 __inline unsigned int AT91F_RTTGetStatus(
1499         AT91PS_RTTC pRTTC)
1500 {
1501         return(pRTTC->RTTC_RTSR);
1502 }
1503
1504 //*--------------------------------------------------------------------------------------
1505 //* \fn     AT91F_RTT_ReadValue()
1506 //* \brief  Read the RTT value
1507 //*--------------------------------------------------------------------------------------
1508 __inline unsigned int AT91F_RTTReadValue(
1509         AT91PS_RTTC pRTTC)
1510 {
1511         register volatile unsigned int val1,val2;
1512         do
1513         {
1514                 val1 = pRTTC->RTTC_RTVR;
1515                 val2 = pRTTC->RTTC_RTVR;
1516         }
1517         while(val1 != val2);
1518         return(val1);
1519 }
1520 /* *****************************************************************************
1521                 SOFTWARE API FOR PITC
1522    ***************************************************************************** */
1523 //*----------------------------------------------------------------------------
1524 //* \fn    AT91F_PITInit
1525 //* \brief System timer init : period in second, system clock freq in MHz
1526 //*----------------------------------------------------------------------------
1527 __inline void AT91F_PITInit(
1528         AT91PS_PITC pPITC,
1529         unsigned int period,
1530         unsigned int pit_frequency)
1531 {
1532         pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10
1533         pPITC->PITC_PIMR |= AT91C_PITC_PITEN;
1534 }
1535
1536 //*----------------------------------------------------------------------------
1537 //* \fn    AT91F_PITSetPIV
1538 //* \brief Set the PIT Periodic Interval Value
1539 //*----------------------------------------------------------------------------
1540 __inline void AT91F_PITSetPIV(
1541         AT91PS_PITC pPITC,
1542         unsigned int piv)
1543 {
1544         pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN));
1545 }
1546
1547 //*----------------------------------------------------------------------------
1548 //* \fn    AT91F_PITEnableInt
1549 //* \brief Enable PIT periodic interrupt
1550 //*----------------------------------------------------------------------------
1551 __inline void AT91F_PITEnableInt(
1552         AT91PS_PITC pPITC)
1553 {
1554         pPITC->PITC_PIMR |= AT91C_PITC_PITIEN;
1555 }
1556
1557 //*----------------------------------------------------------------------------
1558 //* \fn    AT91F_PITDisableInt
1559 //* \brief Disable PIT periodic interrupt
1560 //*----------------------------------------------------------------------------
1561 __inline void AT91F_PITDisableInt(
1562         AT91PS_PITC pPITC)
1563 {
1564         pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;
1565 }
1566
1567 //*----------------------------------------------------------------------------
1568 //* \fn    AT91F_PITGetMode
1569 //* \brief Read PIT mode register
1570 //*----------------------------------------------------------------------------
1571 __inline unsigned int AT91F_PITGetMode(
1572         AT91PS_PITC pPITC)
1573 {
1574         return(pPITC->PITC_PIMR);
1575 }
1576
1577 //*----------------------------------------------------------------------------
1578 //* \fn    AT91F_PITGetStatus
1579 //* \brief Read PIT status register
1580 //*----------------------------------------------------------------------------
1581 __inline unsigned int AT91F_PITGetStatus(
1582         AT91PS_PITC pPITC)
1583 {
1584         return(pPITC->PITC_PISR);
1585 }
1586
1587 //*----------------------------------------------------------------------------
1588 //* \fn    AT91F_PITGetPIIR
1589 //* \brief Read PIT CPIV and PICNT without ressetting the counters
1590 //*----------------------------------------------------------------------------
1591 __inline unsigned int AT91F_PITGetPIIR(
1592         AT91PS_PITC pPITC)
1593 {
1594         return(pPITC->PITC_PIIR);
1595 }
1596
1597 //*----------------------------------------------------------------------------
1598 //* \fn    AT91F_PITGetPIVR
1599 //* \brief Read System timer CPIV and PICNT without ressetting the counters
1600 //*----------------------------------------------------------------------------
1601 __inline unsigned int AT91F_PITGetPIVR(
1602         AT91PS_PITC pPITC)
1603 {
1604         return(pPITC->PITC_PIVR);
1605 }
1606 /* *****************************************************************************
1607                 SOFTWARE API FOR WDTC
1608    ***************************************************************************** */
1609 //*----------------------------------------------------------------------------
1610 //* \fn    AT91F_WDTSetMode
1611 //* \brief Set Watchdog Mode Register
1612 //*----------------------------------------------------------------------------
1613 __inline void AT91F_WDTSetMode(
1614         AT91PS_WDTC pWDTC,
1615         unsigned int Mode)
1616 {
1617         pWDTC->WDTC_WDMR = Mode;
1618 }
1619
1620 //*----------------------------------------------------------------------------
1621 //* \fn    AT91F_WDTRestart
1622 //* \brief Restart Watchdog
1623 //*----------------------------------------------------------------------------
1624 __inline void AT91F_WDTRestart(
1625         AT91PS_WDTC pWDTC)
1626 {
1627         pWDTC->WDTC_WDCR = 0xA5000001;
1628 }
1629
1630 //*----------------------------------------------------------------------------
1631 //* \fn    AT91F_WDTSGettatus
1632 //* \brief Get Watchdog Status
1633 //*----------------------------------------------------------------------------
1634 __inline unsigned int AT91F_WDTSGettatus(
1635         AT91PS_WDTC pWDTC)
1636 {
1637         return(pWDTC->WDTC_WDSR & 0x3);
1638 }
1639
1640 //*----------------------------------------------------------------------------
1641 //* \fn    AT91F_WDTGetPeriod
1642 //* \brief Translate ms into Watchdog Compatible value
1643 //*----------------------------------------------------------------------------
1644 __inline unsigned int AT91F_WDTGetPeriod(unsigned int ms)
1645 {
1646         if ((ms < 4) || (ms > 16000))
1647                 return 0;
1648         return((ms << 8) / 1000);
1649 }
1650 /* *****************************************************************************
1651                 SOFTWARE API FOR VREG
1652    ***************************************************************************** */
1653 //*----------------------------------------------------------------------------
1654 //* \fn    AT91F_VREG_Enable_LowPowerMode
1655 //* \brief Enable VREG Low Power Mode
1656 //*----------------------------------------------------------------------------
1657 __inline void AT91F_VREG_Enable_LowPowerMode(
1658         AT91PS_VREG pVREG)
1659 {
1660         pVREG->VREG_MR |= AT91C_VREG_PSTDBY;
1661 }
1662
1663 //*----------------------------------------------------------------------------
1664 //* \fn    AT91F_VREG_Disable_LowPowerMode
1665 //* \brief Disable VREG Low Power Mode
1666 //*----------------------------------------------------------------------------
1667 __inline void AT91F_VREG_Disable_LowPowerMode(
1668         AT91PS_VREG pVREG)
1669 {
1670         pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY;
1671 }/* *****************************************************************************
1672                 SOFTWARE API FOR MC
1673    ***************************************************************************** */
1674
1675 #define AT91C_MC_CORRECT_KEY  ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key
1676
1677 //*----------------------------------------------------------------------------
1678 //* \fn    AT91F_MC_Remap
1679 //* \brief Make Remap
1680 //*----------------------------------------------------------------------------
1681 __inline void AT91F_MC_Remap (void)     //
1682 {
1683     AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;
1684
1685     pMC->MC_RCR = AT91C_MC_RCB;
1686 }
1687
1688 //*----------------------------------------------------------------------------
1689 //* \fn    AT91F_MC_EFC_CfgModeReg
1690 //* \brief Configure the EFC Mode Register of the MC controller
1691 //*----------------------------------------------------------------------------
1692 __inline void AT91F_MC_EFC_CfgModeReg (
1693         AT91PS_MC pMC, // pointer to a MC controller
1694         unsigned int mode)        // mode register
1695 {
1696         // Write to the FMR register
1697         pMC->MC_FMR = mode;
1698 }
1699
1700 //*----------------------------------------------------------------------------
1701 //* \fn    AT91F_MC_EFC_GetModeReg
1702 //* \brief Return MC EFC Mode Regsiter
1703 //*----------------------------------------------------------------------------
1704 __inline unsigned int AT91F_MC_EFC_GetModeReg(
1705         AT91PS_MC pMC) // pointer to a MC controller
1706 {
1707         return pMC->MC_FMR;
1708 }
1709
1710 //*----------------------------------------------------------------------------
1711 //* \fn    AT91F_MC_EFC_ComputeFMCN
1712 //* \brief Return MC EFC Mode Regsiter
1713 //*----------------------------------------------------------------------------
1714 __inline unsigned int AT91F_MC_EFC_ComputeFMCN(
1715         int master_clock) // master clock in Hz
1716 {
1717         return (master_clock/1000000 +2);
1718 }
1719
1720 //*----------------------------------------------------------------------------
1721 //* \fn    AT91F_MC_EFC_PerformCmd
1722 //* \brief Perform EFC Command
1723 //*----------------------------------------------------------------------------
1724 __inline void AT91F_MC_EFC_PerformCmd (
1725         AT91PS_MC pMC, // pointer to a MC controller
1726     unsigned int transfer_cmd)
1727 {
1728         pMC->MC_FCR = transfer_cmd;
1729 }
1730
1731 //*----------------------------------------------------------------------------
1732 //* \fn    AT91F_MC_EFC_GetStatus
1733 //* \brief Return MC EFC Status
1734 //*----------------------------------------------------------------------------
1735 __inline unsigned int AT91F_MC_EFC_GetStatus(
1736         AT91PS_MC pMC) // pointer to a MC controller
1737 {
1738         return pMC->MC_FSR;
1739 }
1740
1741 //*----------------------------------------------------------------------------
1742 //* \fn    AT91F_MC_EFC_IsInterruptMasked
1743 //* \brief Test if EFC MC Interrupt is Masked
1744 //*----------------------------------------------------------------------------
1745 __inline unsigned int AT91F_MC_EFC_IsInterruptMasked(
1746         AT91PS_MC pMC,   // \arg  pointer to a MC controller
1747         unsigned int flag) // \arg  flag to be tested
1748 {
1749         return (AT91F_MC_EFC_GetModeReg(pMC) & flag);
1750 }
1751
1752 //*----------------------------------------------------------------------------
1753 //* \fn    AT91F_MC_EFC_IsInterruptSet
1754 //* \brief Test if EFC MC Interrupt is Set
1755 //*----------------------------------------------------------------------------
1756 __inline unsigned int AT91F_MC_EFC_IsInterruptSet(
1757         AT91PS_MC pMC,   // \arg  pointer to a MC controller
1758         unsigned int flag) // \arg  flag to be tested
1759 {
1760         return (AT91F_MC_EFC_GetStatus(pMC) & flag);
1761 }
1762
1763 /* *****************************************************************************
1764                 SOFTWARE API FOR SPI
1765    ***************************************************************************** */
1766 //*----------------------------------------------------------------------------
1767 //* \fn    AT91F_SPI_CfgCs
1768 //* \brief Configure SPI chip select register
1769 //*----------------------------------------------------------------------------
1770 __inline void AT91F_SPI_CfgCs (
1771         AT91PS_SPI pSPI,     // pointer to a SPI controller
1772         int cs,     // SPI cs number (0 to 3)
1773         int val)   //  chip select register
1774 {
1775         //* Write to the CSR register
1776         *(pSPI->SPI_CSR + cs) = val;
1777 }
1778
1779 //*----------------------------------------------------------------------------
1780 //* \fn    AT91F_SPI_EnableIt
1781 //* \brief Enable SPI interrupt
1782 //*----------------------------------------------------------------------------
1783 __inline void AT91F_SPI_EnableIt (
1784         AT91PS_SPI pSPI,     // pointer to a SPI controller
1785         unsigned int flag)   // IT to be enabled
1786 {
1787         //* Write to the IER register
1788         pSPI->SPI_IER = flag;
1789 }
1790
1791 //*----------------------------------------------------------------------------
1792 //* \fn    AT91F_SPI_DisableIt
1793 //* \brief Disable SPI interrupt
1794 //*----------------------------------------------------------------------------
1795 __inline void AT91F_SPI_DisableIt (
1796         AT91PS_SPI pSPI, // pointer to a SPI controller
1797         unsigned int flag) // IT to be disabled
1798 {
1799         //* Write to the IDR register
1800         pSPI->SPI_IDR = flag;
1801 }
1802
1803 //*----------------------------------------------------------------------------
1804 //* \fn    AT91F_SPI_Reset
1805 //* \brief Reset the SPI controller
1806 //*----------------------------------------------------------------------------
1807 __inline void AT91F_SPI_Reset (
1808         AT91PS_SPI pSPI // pointer to a SPI controller
1809         )
1810 {
1811         //* Write to the CR register
1812         pSPI->SPI_CR = AT91C_SPI_SWRST;
1813 }
1814
1815 //*----------------------------------------------------------------------------
1816 //* \fn    AT91F_SPI_Enable
1817 //* \brief Enable the SPI controller
1818 //*----------------------------------------------------------------------------
1819 __inline void AT91F_SPI_Enable (
1820         AT91PS_SPI pSPI // pointer to a SPI controller
1821         )
1822 {
1823         //* Write to the CR register
1824         pSPI->SPI_CR = AT91C_SPI_SPIEN;
1825 }
1826
1827 //*----------------------------------------------------------------------------
1828 //* \fn    AT91F_SPI_Disable
1829 //* \brief Disable the SPI controller
1830 //*----------------------------------------------------------------------------
1831 __inline void AT91F_SPI_Disable (
1832         AT91PS_SPI pSPI // pointer to a SPI controller
1833         )
1834 {
1835         //* Write to the CR register
1836         pSPI->SPI_CR = AT91C_SPI_SPIDIS;
1837 }
1838
1839 //*----------------------------------------------------------------------------
1840 //* \fn    AT91F_SPI_CfgMode
1841 //* \brief Enable the SPI controller
1842 //*----------------------------------------------------------------------------
1843 __inline void AT91F_SPI_CfgMode (
1844         AT91PS_SPI pSPI, // pointer to a SPI controller
1845         int mode)        // mode register
1846 {
1847         //* Write to the MR register
1848         pSPI->SPI_MR = mode;
1849 }
1850
1851 //*----------------------------------------------------------------------------
1852 //* \fn    AT91F_SPI_CfgPCS
1853 //* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected
1854 //*----------------------------------------------------------------------------
1855 __inline void AT91F_SPI_CfgPCS (
1856         AT91PS_SPI pSPI, // pointer to a SPI controller
1857         char PCS_Device) // PCS of the Device
1858 {
1859         //* Write to the MR register
1860         pSPI->SPI_MR &= 0xFFF0FFFF;
1861         pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );
1862 }
1863
1864 //*----------------------------------------------------------------------------
1865 //* \fn    AT91F_SPI_ReceiveFrame
1866 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
1867 //*----------------------------------------------------------------------------
1868 __inline unsigned int AT91F_SPI_ReceiveFrame (
1869         AT91PS_SPI pSPI,
1870         char *pBuffer,
1871         unsigned int szBuffer,
1872         char *pNextBuffer,
1873         unsigned int szNextBuffer )
1874 {
1875         return AT91F_PDC_ReceiveFrame(
1876                 (AT91PS_PDC) &(pSPI->SPI_RPR),
1877                 pBuffer,
1878                 szBuffer,
1879                 pNextBuffer,
1880                 szNextBuffer);
1881 }
1882
1883 //*----------------------------------------------------------------------------
1884 //* \fn    AT91F_SPI_SendFrame
1885 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
1886 //*----------------------------------------------------------------------------
1887 __inline unsigned int AT91F_SPI_SendFrame(
1888         AT91PS_SPI pSPI,
1889         char *pBuffer,
1890         unsigned int szBuffer,
1891         char *pNextBuffer,
1892         unsigned int szNextBuffer )
1893 {
1894         return AT91F_PDC_SendFrame(
1895                 (AT91PS_PDC) &(pSPI->SPI_RPR),
1896                 pBuffer,
1897                 szBuffer,
1898                 pNextBuffer,
1899                 szNextBuffer);
1900 }
1901
1902 //*----------------------------------------------------------------------------
1903 //* \fn    AT91F_SPI_Close
1904 //* \brief Close SPI: disable IT disable transfert, close PDC
1905 //*----------------------------------------------------------------------------
1906 __inline void AT91F_SPI_Close (
1907         AT91PS_SPI pSPI)     // \arg pointer to a SPI controller
1908 {
1909     //* Reset all the Chip Select register
1910     pSPI->SPI_CSR[0] = 0 ;
1911     pSPI->SPI_CSR[1] = 0 ;
1912     pSPI->SPI_CSR[2] = 0 ;
1913     pSPI->SPI_CSR[3] = 0 ;
1914
1915     //* Reset the SPI mode
1916     pSPI->SPI_MR = 0  ;
1917
1918     //* Disable all interrupts
1919     pSPI->SPI_IDR = 0xFFFFFFFF ;
1920
1921     //* Abort the Peripheral Data Transfers
1922     AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));
1923
1924     //* Disable receiver and transmitter and stop any activity immediately
1925     pSPI->SPI_CR = AT91C_SPI_SPIDIS;
1926 }
1927
1928 //*----------------------------------------------------------------------------
1929 //* \fn    AT91F_SPI_PutChar
1930 //* \brief Send a character,does not check if ready to send
1931 //*----------------------------------------------------------------------------
1932 __inline void AT91F_SPI_PutChar (
1933         AT91PS_SPI pSPI,
1934         unsigned int character,
1935              unsigned int cs_number )
1936 {
1937     unsigned int value_for_cs;
1938     value_for_cs = (~(1 << cs_number)) & 0xF;  //Place a zero among a 4 ONEs number
1939     pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);
1940 }
1941
1942 //*----------------------------------------------------------------------------
1943 //* \fn    AT91F_SPI_GetChar
1944 //* \brief Receive a character,does not check if a character is available
1945 //*----------------------------------------------------------------------------
1946 __inline int AT91F_SPI_GetChar (
1947         const AT91PS_SPI pSPI)
1948 {
1949     return((pSPI->SPI_RDR) & 0xFFFF);
1950 }
1951
1952 //*----------------------------------------------------------------------------
1953 //* \fn    AT91F_SPI_GetInterruptMaskStatus
1954 //* \brief Return SPI Interrupt Mask Status
1955 //*----------------------------------------------------------------------------
1956 __inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status
1957         AT91PS_SPI pSpi) // \arg  pointer to a SPI controller
1958 {
1959         return pSpi->SPI_IMR;
1960 }
1961
1962 //*----------------------------------------------------------------------------
1963 //* \fn    AT91F_SPI_IsInterruptMasked
1964 //* \brief Test if SPI Interrupt is Masked
1965 //*----------------------------------------------------------------------------
1966 __inline int AT91F_SPI_IsInterruptMasked(
1967         AT91PS_SPI pSpi,   // \arg  pointer to a SPI controller
1968         unsigned int flag) // \arg  flag to be tested
1969 {
1970         return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);
1971 }
1972
1973 /* *****************************************************************************
1974                 SOFTWARE API FOR USART
1975    ***************************************************************************** */
1976 //*----------------------------------------------------------------------------
1977 //* \fn    AT91F_US_Baudrate
1978 //* \brief Calculate the baudrate
1979 //* Standard Asynchronous Mode : 8 bits , 1 stop , no parity
1980 #define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \
1981                         AT91C_US_NBSTOP_1_BIT + \
1982                         AT91C_US_PAR_NONE + \
1983                         AT91C_US_CHRL_8_BITS + \
1984                         AT91C_US_CLKS_CLOCK )
1985
1986 //* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity
1987 #define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \
1988                             AT91C_US_NBSTOP_1_BIT + \
1989                             AT91C_US_PAR_NONE + \
1990                             AT91C_US_CHRL_8_BITS + \
1991                             AT91C_US_CLKS_EXT )
1992
1993 //* Standard Synchronous Mode : 8 bits , 1 stop , no parity
1994 #define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \
1995                        AT91C_US_USMODE_NORMAL + \
1996                        AT91C_US_NBSTOP_1_BIT + \
1997                        AT91C_US_PAR_NONE + \
1998                        AT91C_US_CHRL_8_BITS + \
1999                        AT91C_US_CLKS_CLOCK )
2000
2001 //* SCK used Label
2002 #define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)
2003
2004 //* Standard ISO T=0 Mode : 8 bits , 1 stop , parity
2005 #define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \
2006                                                          AT91C_US_CLKS_CLOCK +\
2007                                  AT91C_US_NBSTOP_1_BIT + \
2008                                  AT91C_US_PAR_EVEN + \
2009                                  AT91C_US_CHRL_8_BITS + \
2010                                  AT91C_US_CKLO +\
2011                                  AT91C_US_OVER)
2012
2013 //* Standard IRDA mode
2014 #define AT91C_US_ASYNC_IRDA_MODE (  AT91C_US_USMODE_IRDA + \
2015                             AT91C_US_NBSTOP_1_BIT + \
2016                             AT91C_US_PAR_NONE + \
2017                             AT91C_US_CHRL_8_BITS + \
2018                             AT91C_US_CLKS_CLOCK )
2019
2020 //*----------------------------------------------------------------------------
2021 //* \fn    AT91F_US_Baudrate
2022 //* \brief Caluculate baud_value according to the main clock and the baud rate
2023 //*----------------------------------------------------------------------------
2024 __inline unsigned int AT91F_US_Baudrate (
2025         const unsigned int main_clock, // \arg peripheral clock
2026         const unsigned int baud_rate)  // \arg UART baudrate
2027 {
2028         unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));
2029         if ((baud_value % 10) >= 5)
2030                 baud_value = (baud_value / 10) + 1;
2031         else
2032                 baud_value /= 10;
2033         return baud_value;
2034 }
2035
2036 //*----------------------------------------------------------------------------
2037 //* \fn    AT91F_US_SetBaudrate
2038 //* \brief Set the baudrate according to the CPU clock
2039 //*----------------------------------------------------------------------------
2040 __inline void AT91F_US_SetBaudrate (
2041         AT91PS_USART pUSART,    // \arg pointer to a USART controller
2042         unsigned int mainClock, // \arg peripheral clock
2043         unsigned int speed)     // \arg UART baudrate
2044 {
2045         //* Define the baud rate divisor register
2046         pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);
2047 }
2048
2049 //*----------------------------------------------------------------------------
2050 //* \fn    AT91F_US_SetTimeguard
2051 //* \brief Set USART timeguard
2052 //*----------------------------------------------------------------------------
2053 __inline void AT91F_US_SetTimeguard (
2054         AT91PS_USART pUSART,    // \arg pointer to a USART controller
2055         unsigned int timeguard) // \arg timeguard value
2056 {
2057         //* Write the Timeguard Register
2058         pUSART->US_TTGR = timeguard ;
2059 }
2060
2061 //*----------------------------------------------------------------------------
2062 //* \fn    AT91F_US_EnableIt
2063 //* \brief Enable USART IT
2064 //*----------------------------------------------------------------------------
2065 __inline void AT91F_US_EnableIt (
2066         AT91PS_USART pUSART, // \arg pointer to a USART controller
2067         unsigned int flag)   // \arg IT to be enabled
2068 {
2069         //* Write to the IER register
2070         pUSART->US_IER = flag;
2071 }
2072
2073 //*----------------------------------------------------------------------------
2074 //* \fn    AT91F_US_DisableIt
2075 //* \brief Disable USART IT
2076 //*----------------------------------------------------------------------------
2077 __inline void AT91F_US_DisableIt (
2078         AT91PS_USART pUSART, // \arg pointer to a USART controller
2079         unsigned int flag)   // \arg IT to be disabled
2080 {
2081         //* Write to the IER register
2082         pUSART->US_IDR = flag;
2083 }
2084
2085 //*----------------------------------------------------------------------------
2086 //* \fn    AT91F_US_Configure
2087 //* \brief Configure USART
2088 //*----------------------------------------------------------------------------
2089 __inline void AT91F_US_Configure (
2090         AT91PS_USART pUSART,     // \arg pointer to a USART controller
2091         unsigned int mainClock,  // \arg peripheral clock
2092         unsigned int mode ,      // \arg mode Register to be programmed
2093         unsigned int baudRate ,  // \arg baudrate to be programmed
2094         unsigned int timeguard ) // \arg timeguard to be programmed
2095 {
2096     //* Disable interrupts
2097     pUSART->US_IDR = (unsigned int) -1;
2098
2099     //* Reset receiver and transmitter
2100     pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;
2101
2102         //* Define the baud rate divisor register
2103         AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);
2104
2105         //* Write the Timeguard Register
2106         AT91F_US_SetTimeguard(pUSART, timeguard);
2107
2108     //* Clear Transmit and Receive Counters
2109     AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));
2110
2111     //* Define the USART mode
2112     pUSART->US_MR = mode  ;
2113
2114 }
2115
2116 //*----------------------------------------------------------------------------
2117 //* \fn    AT91F_US_EnableRx
2118 //* \brief Enable receiving characters
2119 //*----------------------------------------------------------------------------
2120 __inline void AT91F_US_EnableRx (
2121         AT91PS_USART pUSART)     // \arg pointer to a USART controller
2122 {
2123     //* Enable receiver
2124     pUSART->US_CR = AT91C_US_RXEN;
2125 }
2126
2127 //*----------------------------------------------------------------------------
2128 //* \fn    AT91F_US_EnableTx
2129 //* \brief Enable sending characters
2130 //*----------------------------------------------------------------------------
2131 __inline void AT91F_US_EnableTx (
2132         AT91PS_USART pUSART)     // \arg pointer to a USART controller
2133 {
2134     //* Enable  transmitter
2135     pUSART->US_CR = AT91C_US_TXEN;
2136 }
2137
2138 //*----------------------------------------------------------------------------
2139 //* \fn    AT91F_US_ResetRx
2140 //* \brief Reset Receiver and re-enable it
2141 //*----------------------------------------------------------------------------
2142 __inline void AT91F_US_ResetRx (
2143         AT91PS_USART pUSART)     // \arg pointer to a USART controller
2144 {
2145         //* Reset receiver
2146         pUSART->US_CR = AT91C_US_RSTRX;
2147     //* Re-Enable receiver
2148     pUSART->US_CR = AT91C_US_RXEN;
2149 }
2150
2151 //*----------------------------------------------------------------------------
2152 //* \fn    AT91F_US_ResetTx
2153 //* \brief Reset Transmitter and re-enable it
2154 //*----------------------------------------------------------------------------
2155 __inline void AT91F_US_ResetTx (
2156         AT91PS_USART pUSART)     // \arg pointer to a USART controller
2157 {
2158         //* Reset transmitter
2159         pUSART->US_CR = AT91C_US_RSTTX;
2160     //* Enable transmitter
2161     pUSART->US_CR = AT91C_US_TXEN;
2162 }
2163
2164 //*----------------------------------------------------------------------------
2165 //* \fn    AT91F_US_DisableRx
2166 //* \brief Disable Receiver
2167 //*----------------------------------------------------------------------------
2168 __inline void AT91F_US_DisableRx (
2169         AT91PS_USART pUSART)     // \arg pointer to a USART controller
2170 {
2171     //* Disable receiver
2172     pUSART->US_CR = AT91C_US_RXDIS;
2173 }
2174
2175 //*----------------------------------------------------------------------------
2176 //* \fn    AT91F_US_DisableTx
2177 //* \brief Disable Transmitter
2178 //*----------------------------------------------------------------------------
2179 __inline void AT91F_US_DisableTx (
2180         AT91PS_USART pUSART)     // \arg pointer to a USART controller
2181 {
2182     //* Disable transmitter
2183     pUSART->US_CR = AT91C_US_TXDIS;
2184 }
2185
2186 //*----------------------------------------------------------------------------
2187 //* \fn    AT91F_US_Close
2188 //* \brief Close USART: disable IT disable receiver and transmitter, close PDC
2189 //*----------------------------------------------------------------------------
2190 __inline void AT91F_US_Close (
2191         AT91PS_USART pUSART)     // \arg pointer to a USART controller
2192 {
2193     //* Reset the baud rate divisor register
2194     pUSART->US_BRGR = 0 ;
2195
2196     //* Reset the USART mode
2197     pUSART->US_MR = 0  ;
2198
2199     //* Reset the Timeguard Register
2200     pUSART->US_TTGR = 0;
2201
2202     //* Disable all interrupts
2203     pUSART->US_IDR = 0xFFFFFFFF ;
2204
2205     //* Abort the Peripheral Data Transfers
2206     AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));
2207
2208     //* Disable receiver and transmitter and stop any activity immediately
2209     pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;
2210 }
2211
2212 //*----------------------------------------------------------------------------
2213 //* \fn    AT91F_US_TxReady
2214 //* \brief Return 1 if a character can be written in US_THR
2215 //*----------------------------------------------------------------------------
2216 __inline unsigned int AT91F_US_TxReady (
2217         AT91PS_USART pUSART )     // \arg pointer to a USART controller
2218 {
2219     return (pUSART->US_CSR & AT91C_US_TXRDY);
2220 }
2221
2222 //*----------------------------------------------------------------------------
2223 //* \fn    AT91F_US_RxReady
2224 //* \brief Return 1 if a character can be read in US_RHR
2225 //*----------------------------------------------------------------------------
2226 __inline unsigned int AT91F_US_RxReady (
2227         AT91PS_USART pUSART )     // \arg pointer to a USART controller
2228 {
2229     return (pUSART->US_CSR & AT91C_US_RXRDY);
2230 }
2231
2232 //*----------------------------------------------------------------------------
2233 //* \fn    AT91F_US_Error
2234 //* \brief Return the error flag
2235 //*----------------------------------------------------------------------------
2236 __inline unsigned int AT91F_US_Error (
2237         AT91PS_USART pUSART )     // \arg pointer to a USART controller
2238 {
2239     return (pUSART->US_CSR &
2240         (AT91C_US_OVRE |  // Overrun error
2241          AT91C_US_FRAME | // Framing error
2242          AT91C_US_PARE));  // Parity error
2243 }
2244
2245 //*----------------------------------------------------------------------------
2246 //* \fn    AT91F_US_PutChar
2247 //* \brief Send a character,does not check if ready to send
2248 //*----------------------------------------------------------------------------
2249 __inline void AT91F_US_PutChar (
2250         AT91PS_USART pUSART,
2251         int character )
2252 {
2253     pUSART->US_THR = (character & 0x1FF);
2254 }
2255
2256 //*----------------------------------------------------------------------------
2257 //* \fn    AT91F_US_GetChar
2258 //* \brief Receive a character,does not check if a character is available
2259 //*----------------------------------------------------------------------------
2260 __inline int AT91F_US_GetChar (
2261         const AT91PS_USART pUSART)
2262 {
2263     return((pUSART->US_RHR) & 0x1FF);
2264 }
2265
2266 //*----------------------------------------------------------------------------
2267 //* \fn    AT91F_US_SendFrame
2268 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
2269 //*----------------------------------------------------------------------------
2270 __inline unsigned int AT91F_US_SendFrame(
2271         AT91PS_USART pUSART,
2272         char *pBuffer,
2273         unsigned int szBuffer,
2274         char *pNextBuffer,
2275         unsigned int szNextBuffer )
2276 {
2277         return AT91F_PDC_SendFrame(
2278                 (AT91PS_PDC) &(pUSART->US_RPR),
2279                 pBuffer,
2280                 szBuffer,
2281                 pNextBuffer,
2282                 szNextBuffer);
2283 }
2284
2285 //*----------------------------------------------------------------------------
2286 //* \fn    AT91F_US_ReceiveFrame
2287 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
2288 //*----------------------------------------------------------------------------
2289 __inline unsigned int AT91F_US_ReceiveFrame (
2290         AT91PS_USART pUSART,
2291         char *pBuffer,
2292         unsigned int szBuffer,
2293         char *pNextBuffer,
2294         unsigned int szNextBuffer )
2295 {
2296         return AT91F_PDC_ReceiveFrame(
2297                 (AT91PS_PDC) &(pUSART->US_RPR),
2298                 pBuffer,
2299                 szBuffer,
2300                 pNextBuffer,
2301                 szNextBuffer);
2302 }
2303
2304 //*----------------------------------------------------------------------------
2305 //* \fn    AT91F_US_SetIrdaFilter
2306 //* \brief Set the value of IrDa filter tregister
2307 //*----------------------------------------------------------------------------
2308 __inline void AT91F_US_SetIrdaFilter (
2309         AT91PS_USART pUSART,
2310         unsigned char value
2311 )
2312 {
2313         pUSART->US_IF = value;
2314 }
2315
2316 /* *****************************************************************************
2317                 SOFTWARE API FOR SSC
2318    ***************************************************************************** */
2319 //* Define the standard I2S mode configuration
2320
2321 //* Configuration to set in the SSC Transmit Clock Mode Register
2322 //* Parameters :  nb_bit_by_slot : 8, 16 or 32 bits
2323 //*                       nb_slot_by_frame : number of channels
2324 #define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
2325                                                                            AT91C_SSC_CKS_DIV   +\
2326                                            AT91C_SSC_CKO_CONTINOUS      +\
2327                                            AT91C_SSC_CKG_NONE    +\
2328                                        AT91C_SSC_START_FALL_RF +\
2329                                                    AT91C_SSC_STTOUT  +\
2330                                            ((1<<16) & AT91C_SSC_STTDLY) +\
2331                                            ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))
2332
2333
2334 //* Configuration to set in the SSC Transmit Frame Mode Register
2335 //* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
2336 //*                      nb_slot_by_frame : number of channels
2337 #define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
2338                                                                         (nb_bit_by_slot-1)  +\
2339                                         AT91C_SSC_MSBF   +\
2340                                         (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB)  +\
2341                                         (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
2342                                         AT91C_SSC_FSOS_NEGATIVE)
2343
2344
2345 //*----------------------------------------------------------------------------
2346 //* \fn    AT91F_SSC_SetBaudrate
2347 //* \brief Set the baudrate according to the CPU clock
2348 //*----------------------------------------------------------------------------
2349 __inline void AT91F_SSC_SetBaudrate (
2350         AT91PS_SSC pSSC,        // \arg pointer to a SSC controller
2351         unsigned int mainClock, // \arg peripheral clock
2352         unsigned int speed)     // \arg SSC baudrate
2353 {
2354         unsigned int baud_value;
2355         //* Define the baud rate divisor register
2356         if (speed == 0)
2357            baud_value = 0;
2358         else
2359         {
2360            baud_value = (unsigned int) (mainClock * 10)/(2*speed);
2361            if ((baud_value % 10) >= 5)
2362                   baud_value = (baud_value / 10) + 1;
2363            else
2364                   baud_value /= 10;
2365         }
2366
2367         pSSC->SSC_CMR = baud_value;
2368 }
2369
2370 //*----------------------------------------------------------------------------
2371 //* \fn    AT91F_SSC_Configure
2372 //* \brief Configure SSC
2373 //*----------------------------------------------------------------------------
2374 __inline void AT91F_SSC_Configure (
2375              AT91PS_SSC pSSC,          // \arg pointer to a SSC controller
2376              unsigned int syst_clock,  // \arg System Clock Frequency
2377              unsigned int baud_rate,   // \arg Expected Baud Rate Frequency
2378              unsigned int clock_rx,    // \arg Receiver Clock Parameters
2379              unsigned int mode_rx,     // \arg mode Register to be programmed
2380              unsigned int clock_tx,    // \arg Transmitter Clock Parameters
2381              unsigned int mode_tx)     // \arg mode Register to be programmed
2382 {
2383     //* Disable interrupts
2384         pSSC->SSC_IDR = (unsigned int) -1;
2385
2386     //* Reset receiver and transmitter
2387         pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;
2388
2389     //* Define the Clock Mode Register
2390         AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);
2391
2392      //* Write the Receive Clock Mode Register
2393         pSSC->SSC_RCMR =  clock_rx;
2394
2395      //* Write the Transmit Clock Mode Register
2396         pSSC->SSC_TCMR =  clock_tx;
2397
2398      //* Write the Receive Frame Mode Register
2399         pSSC->SSC_RFMR =  mode_rx;
2400
2401      //* Write the Transmit Frame Mode Register
2402         pSSC->SSC_TFMR =  mode_tx;
2403
2404     //* Clear Transmit and Receive Counters
2405         AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));
2406
2407
2408 }
2409
2410 //*----------------------------------------------------------------------------
2411 //* \fn    AT91F_SSC_EnableRx
2412 //* \brief Enable receiving datas
2413 //*----------------------------------------------------------------------------
2414 __inline void AT91F_SSC_EnableRx (
2415         AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
2416 {
2417     //* Enable receiver
2418     pSSC->SSC_CR = AT91C_SSC_RXEN;
2419 }
2420
2421 //*----------------------------------------------------------------------------
2422 //* \fn    AT91F_SSC_DisableRx
2423 //* \brief Disable receiving datas
2424 //*----------------------------------------------------------------------------
2425 __inline void AT91F_SSC_DisableRx (
2426         AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
2427 {
2428     //* Disable receiver
2429     pSSC->SSC_CR = AT91C_SSC_RXDIS;
2430 }
2431
2432 //*----------------------------------------------------------------------------
2433 //* \fn    AT91F_SSC_EnableTx
2434 //* \brief Enable sending datas
2435 //*----------------------------------------------------------------------------
2436 __inline void AT91F_SSC_EnableTx (
2437         AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
2438 {
2439     //* Enable  transmitter
2440     pSSC->SSC_CR = AT91C_SSC_TXEN;
2441 }
2442
2443 //*----------------------------------------------------------------------------
2444 //* \fn    AT91F_SSC_DisableTx
2445 //* \brief Disable sending datas
2446 //*----------------------------------------------------------------------------
2447 __inline void AT91F_SSC_DisableTx (
2448         AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
2449 {
2450     //* Disable  transmitter
2451     pSSC->SSC_CR = AT91C_SSC_TXDIS;
2452 }
2453
2454 //*----------------------------------------------------------------------------
2455 //* \fn    AT91F_SSC_EnableIt
2456 //* \brief Enable SSC IT
2457 //*----------------------------------------------------------------------------
2458 __inline void AT91F_SSC_EnableIt (
2459         AT91PS_SSC pSSC, // \arg pointer to a SSC controller
2460         unsigned int flag)   // \arg IT to be enabled
2461 {
2462         //* Write to the IER register
2463         pSSC->SSC_IER = flag;
2464 }
2465
2466 //*----------------------------------------------------------------------------
2467 //* \fn    AT91F_SSC_DisableIt
2468 //* \brief Disable SSC IT
2469 //*----------------------------------------------------------------------------
2470 __inline void AT91F_SSC_DisableIt (
2471         AT91PS_SSC pSSC, // \arg pointer to a SSC controller
2472         unsigned int flag)   // \arg IT to be disabled
2473 {
2474         //* Write to the IDR register
2475         pSSC->SSC_IDR = flag;
2476 }
2477
2478 //*----------------------------------------------------------------------------
2479 //* \fn    AT91F_SSC_ReceiveFrame
2480 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
2481 //*----------------------------------------------------------------------------
2482 __inline unsigned int AT91F_SSC_ReceiveFrame (
2483         AT91PS_SSC pSSC,
2484         char *pBuffer,
2485         unsigned int szBuffer,
2486         char *pNextBuffer,
2487         unsigned int szNextBuffer )
2488 {
2489         return AT91F_PDC_ReceiveFrame(
2490                 (AT91PS_PDC) &(pSSC->SSC_RPR),
2491                 pBuffer,
2492                 szBuffer,
2493                 pNextBuffer,
2494                 szNextBuffer);
2495 }
2496
2497 //*----------------------------------------------------------------------------
2498 //* \fn    AT91F_SSC_SendFrame
2499 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
2500 //*----------------------------------------------------------------------------
2501 __inline unsigned int AT91F_SSC_SendFrame(
2502         AT91PS_SSC pSSC,
2503         char *pBuffer,
2504         unsigned int szBuffer,
2505         char *pNextBuffer,
2506         unsigned int szNextBuffer )
2507 {
2508         return AT91F_PDC_SendFrame(
2509                 (AT91PS_PDC) &(pSSC->SSC_RPR),
2510                 pBuffer,
2511                 szBuffer,
2512                 pNextBuffer,
2513                 szNextBuffer);
2514 }
2515
2516 //*----------------------------------------------------------------------------
2517 //* \fn    AT91F_SSC_GetInterruptMaskStatus
2518 //* \brief Return SSC Interrupt Mask Status
2519 //*----------------------------------------------------------------------------
2520 __inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status
2521         AT91PS_SSC pSsc) // \arg  pointer to a SSC controller
2522 {
2523         return pSsc->SSC_IMR;
2524 }
2525
2526 //*----------------------------------------------------------------------------
2527 //* \fn    AT91F_SSC_IsInterruptMasked
2528 //* \brief Test if SSC Interrupt is Masked
2529 //*----------------------------------------------------------------------------
2530 __inline int AT91F_SSC_IsInterruptMasked(
2531         AT91PS_SSC pSsc,   // \arg  pointer to a SSC controller
2532         unsigned int flag) // \arg  flag to be tested
2533 {
2534         return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);
2535 }
2536
2537 /* *****************************************************************************
2538                 SOFTWARE API FOR TWI
2539    ***************************************************************************** */
2540 //*----------------------------------------------------------------------------
2541 //* \fn    AT91F_TWI_EnableIt
2542 //* \brief Enable TWI IT
2543 //*----------------------------------------------------------------------------
2544 __inline void AT91F_TWI_EnableIt (
2545         AT91PS_TWI pTWI, // \arg pointer to a TWI controller
2546         unsigned int flag)   // \arg IT to be enabled
2547 {
2548         //* Write to the IER register
2549         pTWI->TWI_IER = flag;
2550 }
2551
2552 //*----------------------------------------------------------------------------
2553 //* \fn    AT91F_TWI_DisableIt
2554 //* \brief Disable TWI IT
2555 //*----------------------------------------------------------------------------
2556 __inline void AT91F_TWI_DisableIt (
2557         AT91PS_TWI pTWI, // \arg pointer to a TWI controller
2558         unsigned int flag)   // \arg IT to be disabled
2559 {
2560         //* Write to the IDR register
2561         pTWI->TWI_IDR = flag;
2562 }
2563
2564 //*----------------------------------------------------------------------------
2565 //* \fn    AT91F_TWI_Configure
2566 //* \brief Configure TWI in master mode
2567 //*----------------------------------------------------------------------------
2568 __inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI )          // \arg pointer to a TWI controller
2569 {
2570     //* Disable interrupts
2571         pTWI->TWI_IDR = (unsigned int) -1;
2572
2573     //* Reset peripheral
2574         pTWI->TWI_CR = AT91C_TWI_SWRST;
2575
2576         //* Set Master mode
2577         pTWI->TWI_CR = AT91C_TWI_MSEN;
2578
2579 }
2580
2581 //*----------------------------------------------------------------------------
2582 //* \fn    AT91F_TWI_GetInterruptMaskStatus
2583 //* \brief Return TWI Interrupt Mask Status
2584 //*----------------------------------------------------------------------------
2585 __inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status
2586         AT91PS_TWI pTwi) // \arg  pointer to a TWI controller
2587 {
2588         return pTwi->TWI_IMR;
2589 }
2590
2591 //*----------------------------------------------------------------------------
2592 //* \fn    AT91F_TWI_IsInterruptMasked
2593 //* \brief Test if TWI Interrupt is Masked
2594 //*----------------------------------------------------------------------------
2595 __inline int AT91F_TWI_IsInterruptMasked(
2596         AT91PS_TWI pTwi,   // \arg  pointer to a TWI controller
2597         unsigned int flag) // \arg  flag to be tested
2598 {
2599         return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);
2600 }
2601
2602 /* *****************************************************************************
2603                 SOFTWARE API FOR PWMC
2604    ***************************************************************************** */
2605 //*----------------------------------------------------------------------------
2606 //* \fn    AT91F_PWM_GetStatus
2607 //* \brief Return PWM Interrupt Status
2608 //*----------------------------------------------------------------------------
2609 __inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status
2610         AT91PS_PWMC pPWM) // pointer to a PWM controller
2611 {
2612         return pPWM->PWMC_SR;
2613 }
2614
2615 //*----------------------------------------------------------------------------
2616 //* \fn    AT91F_PWM_InterruptEnable
2617 //* \brief Enable PWM Interrupt
2618 //*----------------------------------------------------------------------------
2619 __inline void AT91F_PWMC_InterruptEnable(
2620         AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
2621         unsigned int flag) // \arg  PWM interrupt to be enabled
2622 {
2623         pPwm->PWMC_IER = flag;
2624 }
2625
2626 //*----------------------------------------------------------------------------
2627 //* \fn    AT91F_PWM_InterruptDisable
2628 //* \brief Disable PWM Interrupt
2629 //*----------------------------------------------------------------------------
2630 __inline void AT91F_PWMC_InterruptDisable(
2631         AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
2632         unsigned int flag) // \arg  PWM interrupt to be disabled
2633 {
2634         pPwm->PWMC_IDR = flag;
2635 }
2636
2637 //*----------------------------------------------------------------------------
2638 //* \fn    AT91F_PWM_GetInterruptMaskStatus
2639 //* \brief Return PWM Interrupt Mask Status
2640 //*----------------------------------------------------------------------------
2641 __inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status
2642         AT91PS_PWMC pPwm) // \arg  pointer to a PWM controller
2643 {
2644         return pPwm->PWMC_IMR;
2645 }
2646
2647 //*----------------------------------------------------------------------------
2648 //* \fn    AT91F_PWM_IsInterruptMasked
2649 //* \brief Test if PWM Interrupt is Masked
2650 //*----------------------------------------------------------------------------
2651 __inline unsigned int AT91F_PWMC_IsInterruptMasked(
2652         AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
2653         unsigned int flag) // \arg  flag to be tested
2654 {
2655         return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag);
2656 }
2657
2658 //*----------------------------------------------------------------------------
2659 //* \fn    AT91F_PWM_IsStatusSet
2660 //* \brief Test if PWM Interrupt is Set
2661 //*----------------------------------------------------------------------------
2662 __inline unsigned int AT91F_PWMC_IsStatusSet(
2663         AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
2664         unsigned int flag) // \arg  flag to be tested
2665 {
2666         return (AT91F_PWMC_GetStatus(pPWM) & flag);
2667 }
2668
2669 //*----------------------------------------------------------------------------
2670 //* \fn    AT91F_PWM_CfgChannel
2671 //* \brief Test if PWM Interrupt is Set
2672 //*----------------------------------------------------------------------------
2673 __inline void AT91F_PWMC_CfgChannel(
2674         AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
2675         unsigned int channelId, // \arg PWM channel ID
2676         unsigned int mode, // \arg  PWM mode
2677         unsigned int period, // \arg PWM period
2678         unsigned int duty) // \arg PWM duty cycle
2679 {
2680         pPWM->PWMC_CH[channelId].PWMC_CMR = mode;
2681         pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;
2682         pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;
2683 }
2684
2685 //*----------------------------------------------------------------------------
2686 //* \fn    AT91F_PWM_StartChannel
2687 //* \brief Enable channel
2688 //*----------------------------------------------------------------------------
2689 __inline void AT91F_PWMC_StartChannel(
2690         AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
2691         unsigned int flag) // \arg  Channels IDs to be enabled
2692 {
2693         pPWM->PWMC_ENA = flag;
2694 }
2695
2696 //*----------------------------------------------------------------------------
2697 //* \fn    AT91F_PWM_StopChannel
2698 //* \brief Disable channel
2699 //*----------------------------------------------------------------------------
2700 __inline void AT91F_PWMC_StopChannel(
2701         AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
2702         unsigned int flag) // \arg  Channels IDs to be enabled
2703 {
2704         pPWM->PWMC_DIS = flag;
2705 }
2706
2707 //*----------------------------------------------------------------------------
2708 //* \fn    AT91F_PWM_UpdateChannel
2709 //* \brief Update Period or Duty Cycle
2710 //*----------------------------------------------------------------------------
2711 __inline void AT91F_PWMC_UpdateChannel(
2712         AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
2713         unsigned int channelId, // \arg PWM channel ID
2714         unsigned int update) // \arg  Channels IDs to be enabled
2715 {
2716         pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;
2717 }
2718
2719 /* *****************************************************************************
2720                 SOFTWARE API FOR UDP
2721    ***************************************************************************** */
2722 //*----------------------------------------------------------------------------
2723 //* \fn    AT91F_UDP_EnableIt
2724 //* \brief Enable UDP IT
2725 //*----------------------------------------------------------------------------
2726 __inline void AT91F_UDP_EnableIt (
2727         AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
2728         unsigned int flag)   // \arg IT to be enabled
2729 {
2730         //* Write to the IER register
2731         pUDP->UDP_IER = flag;
2732 }
2733
2734 //*----------------------------------------------------------------------------
2735 //* \fn    AT91F_UDP_DisableIt
2736 //* \brief Disable UDP IT
2737 //*----------------------------------------------------------------------------
2738 __inline void AT91F_UDP_DisableIt (
2739         AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
2740         unsigned int flag)   // \arg IT to be disabled
2741 {
2742         //* Write to the IDR register
2743         pUDP->UDP_IDR = flag;
2744 }
2745
2746 //*----------------------------------------------------------------------------
2747 //* \fn    AT91F_UDP_SetAddress
2748 //* \brief Set UDP functional address
2749 //*----------------------------------------------------------------------------
2750 __inline void AT91F_UDP_SetAddress (
2751         AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
2752         unsigned char address)   // \arg new UDP address
2753 {
2754         pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);
2755 }
2756
2757 //*----------------------------------------------------------------------------
2758 //* \fn    AT91F_UDP_EnableEp
2759 //* \brief Enable Endpoint
2760 //*----------------------------------------------------------------------------
2761 __inline void AT91F_UDP_EnableEp (
2762         AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
2763         unsigned char endpoint)   // \arg endpoint number
2764 {
2765         pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS;
2766 }
2767
2768 //*----------------------------------------------------------------------------
2769 //* \fn    AT91F_UDP_DisableEp
2770 //* \brief Enable Endpoint
2771 //*----------------------------------------------------------------------------
2772 __inline void AT91F_UDP_DisableEp (
2773         AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
2774         unsigned char endpoint)   // \arg endpoint number
2775 {
2776         pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS;
2777 }
2778
2779 //*----------------------------------------------------------------------------
2780 //* \fn    AT91F_UDP_SetState
2781 //* \brief Set UDP Device state
2782 //*----------------------------------------------------------------------------
2783 __inline void AT91F_UDP_SetState (
2784         AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
2785         unsigned int flag)   // \arg new UDP address
2786 {
2787         pUDP->UDP_GLBSTATE  &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);
2788         pUDP->UDP_GLBSTATE  |= flag;
2789 }
2790
2791 //*----------------------------------------------------------------------------
2792 //* \fn    AT91F_UDP_GetState
2793 //* \brief return UDP Device state
2794 //*----------------------------------------------------------------------------
2795 __inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state
2796         AT91PS_UDP pUDP)     // \arg pointer to a UDP controller
2797 {
2798         return (pUDP->UDP_GLBSTATE  & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));
2799 }
2800
2801 //*----------------------------------------------------------------------------
2802 //* \fn    AT91F_UDP_ResetEp
2803 //* \brief Reset UDP endpoint
2804 //*----------------------------------------------------------------------------
2805 __inline void AT91F_UDP_ResetEp ( // \return the UDP device state
2806         AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
2807         unsigned int flag)   // \arg Endpoints to be reset
2808 {
2809         pUDP->UDP_RSTEP = flag;
2810         pUDP->UDP_RSTEP = 0;
2811 }
2812
2813 //*----------------------------------------------------------------------------
2814 //* \fn    AT91F_UDP_EpStall
2815 //* \brief Endpoint will STALL requests
2816 //*----------------------------------------------------------------------------
2817 __inline void AT91F_UDP_EpStall(
2818         AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
2819         unsigned char endpoint)   // \arg endpoint number
2820 {
2821         pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;
2822 }
2823
2824 //*----------------------------------------------------------------------------
2825 //* \fn    AT91F_UDP_EpWrite
2826 //* \brief Write value in the DPR
2827 //*----------------------------------------------------------------------------
2828 __inline void AT91F_UDP_EpWrite(
2829         AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
2830         unsigned char endpoint,  // \arg endpoint number
2831         unsigned char value)     // \arg value to be written in the DPR
2832 {
2833         pUDP->UDP_FDR[endpoint] = value;
2834 }
2835
2836 //*----------------------------------------------------------------------------
2837 //* \fn    AT91F_UDP_EpRead
2838 //* \brief Return value from the DPR
2839 //*----------------------------------------------------------------------------
2840 __inline unsigned int AT91F_UDP_EpRead(
2841         AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
2842         unsigned char endpoint)  // \arg endpoint number
2843 {
2844         return pUDP->UDP_FDR[endpoint];
2845 }
2846
2847 //*----------------------------------------------------------------------------
2848 //* \fn    AT91F_UDP_EpEndOfWr
2849 //* \brief Notify the UDP that values in DPR are ready to be sent
2850 //*----------------------------------------------------------------------------
2851 __inline void AT91F_UDP_EpEndOfWr(
2852         AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
2853         unsigned char endpoint)  // \arg endpoint number
2854 {
2855         pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;
2856 }
2857
2858 //*----------------------------------------------------------------------------
2859 //* \fn    AT91F_UDP_EpClear
2860 //* \brief Clear flag in the endpoint CSR register
2861 //*----------------------------------------------------------------------------
2862 __inline void AT91F_UDP_EpClear(
2863         AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
2864         unsigned char endpoint,  // \arg endpoint number
2865         unsigned int flag)       // \arg flag to be cleared
2866 {
2867         pUDP->UDP_CSR[endpoint] &= ~(flag);
2868 }
2869
2870 //*----------------------------------------------------------------------------
2871 //* \fn    AT91F_UDP_EpSet
2872 //* \brief Set flag in the endpoint CSR register
2873 //*----------------------------------------------------------------------------
2874 __inline void AT91F_UDP_EpSet(
2875         AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
2876         unsigned char endpoint,  // \arg endpoint number
2877         unsigned int flag)       // \arg flag to be cleared
2878 {
2879         pUDP->UDP_CSR[endpoint] |= flag;
2880 }
2881
2882 //*----------------------------------------------------------------------------
2883 //* \fn    AT91F_UDP_EpStatus
2884 //* \brief Return the endpoint CSR register
2885 //*----------------------------------------------------------------------------
2886 __inline unsigned int AT91F_UDP_EpStatus(
2887         AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
2888         unsigned char endpoint)  // \arg endpoint number
2889 {
2890         return pUDP->UDP_CSR[endpoint];
2891 }
2892
2893 //*----------------------------------------------------------------------------
2894 //* \fn    AT91F_UDP_GetInterruptMaskStatus
2895 //* \brief Return UDP Interrupt Mask Status
2896 //*----------------------------------------------------------------------------
2897 __inline unsigned int AT91F_UDP_GetInterruptMaskStatus(
2898   AT91PS_UDP pUdp)        // \arg  pointer to a UDP controller
2899 {
2900   return pUdp->UDP_IMR;
2901 }
2902
2903 //*----------------------------------------------------------------------------
2904 //* \fn    AT91F_UDP_IsInterruptMasked
2905 //* \brief Test if UDP Interrupt is Masked
2906 //*----------------------------------------------------------------------------
2907 __inline int AT91F_UDP_IsInterruptMasked(
2908   AT91PS_UDP pUdp,       // \arg  pointer to a UDP controller
2909   unsigned int flag)     // \arg  flag to be tested
2910 {
2911   return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);
2912 }
2913
2914 // ----------------------------------------------------------------------------
2915 //  \fn    AT91F_UDP_InterruptStatusRegister
2916 //  \brief Return the Interrupt Status Register
2917 // ----------------------------------------------------------------------------
2918 __inline unsigned int AT91F_UDP_InterruptStatusRegister(
2919   AT91PS_UDP pUDP )      // \arg  pointer to a UDP controller
2920 {
2921   return pUDP->UDP_ISR;
2922 }
2923
2924 // ----------------------------------------------------------------------------
2925 //  \fn    AT91F_UDP_InterruptClearRegister
2926 //  \brief Clear Interrupt Register
2927 // ----------------------------------------------------------------------------
2928 __inline void AT91F_UDP_InterruptClearRegister (
2929   AT91PS_UDP pUDP,       // \arg pointer to UDP controller
2930   unsigned int flag)     // \arg IT to be cleat
2931 {
2932   pUDP->UDP_ICR = flag;
2933 }
2934
2935 // ----------------------------------------------------------------------------
2936 //  \fn    AT91F_UDP_EnableTransceiver
2937 //  \brief Enable transceiver
2938 // ----------------------------------------------------------------------------
2939 __inline void AT91F_UDP_EnableTransceiver(
2940   AT91PS_UDP pUDP )      // \arg  pointer to a UDP controller
2941 {
2942     pUDP->UDP_TXVC &= ~AT91C_UDP_TXVDIS;
2943 }
2944
2945 // ----------------------------------------------------------------------------
2946 //  \fn    AT91F_UDP_DisableTransceiver
2947 //  \brief Disable transceiver
2948 // ----------------------------------------------------------------------------
2949 __inline void AT91F_UDP_DisableTransceiver(
2950   AT91PS_UDP pUDP )      // \arg  pointer to a UDP controller
2951 {
2952     pUDP->UDP_TXVC = AT91C_UDP_TXVDIS;
2953 }
2954
2955 /* *****************************************************************************
2956                 SOFTWARE API FOR TC
2957    ***************************************************************************** */
2958 //*----------------------------------------------------------------------------
2959 //* \fn    AT91F_TC_InterruptEnable
2960 //* \brief Enable TC Interrupt
2961 //*----------------------------------------------------------------------------
2962 __inline void AT91F_TC_InterruptEnable(
2963         AT91PS_TC pTc,   // \arg  pointer to a TC controller
2964         unsigned int flag) // \arg  TC interrupt to be enabled
2965 {
2966         pTc->TC_IER = flag;
2967 }
2968
2969 //*----------------------------------------------------------------------------
2970 //* \fn    AT91F_TC_InterruptDisable
2971 //* \brief Disable TC Interrupt
2972 //*----------------------------------------------------------------------------
2973 __inline void AT91F_TC_InterruptDisable(
2974         AT91PS_TC pTc,   // \arg  pointer to a TC controller
2975         unsigned int flag) // \arg  TC interrupt to be disabled
2976 {
2977         pTc->TC_IDR = flag;
2978 }
2979
2980 //*----------------------------------------------------------------------------
2981 //* \fn    AT91F_TC_GetInterruptMaskStatus
2982 //* \brief Return TC Interrupt Mask Status
2983 //*----------------------------------------------------------------------------
2984 __inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status
2985         AT91PS_TC pTc) // \arg  pointer to a TC controller
2986 {
2987         return pTc->TC_IMR;
2988 }
2989
2990 //*----------------------------------------------------------------------------
2991 //* \fn    AT91F_TC_IsInterruptMasked
2992 //* \brief Test if TC Interrupt is Masked
2993 //*----------------------------------------------------------------------------
2994 __inline int AT91F_TC_IsInterruptMasked(
2995         AT91PS_TC pTc,   // \arg  pointer to a TC controller
2996         unsigned int flag) // \arg  flag to be tested
2997 {
2998         return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);
2999 }
3000
3001 /* *****************************************************************************
3002                 SOFTWARE API FOR CAN
3003    ***************************************************************************** */
3004 #define STANDARD_FORMAT 0
3005 #define EXTENDED_FORMAT 1
3006
3007 //*----------------------------------------------------------------------------
3008 //* \fn    AT91F_InitMailboxRegisters()
3009 //* \brief Configure the corresponding mailbox
3010 //*----------------------------------------------------------------------------
3011 __inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB  CAN_Mailbox,
3012                                                                 int                     mode_reg,
3013                                                                 int                     acceptance_mask_reg,
3014                                                                 int                     id_reg,
3015                                                                 int                     data_low_reg,
3016                                                                 int                     data_high_reg,
3017                                                                 int                     control_reg)
3018 {
3019         CAN_Mailbox->CAN_MB_MCR         = 0x0;
3020         CAN_Mailbox->CAN_MB_MMR         = mode_reg;
3021         CAN_Mailbox->CAN_MB_MAM         = acceptance_mask_reg;
3022         CAN_Mailbox->CAN_MB_MID         = id_reg;
3023         CAN_Mailbox->CAN_MB_MDL         = data_low_reg;
3024         CAN_Mailbox->CAN_MB_MDH         = data_high_reg;
3025         CAN_Mailbox->CAN_MB_MCR         = control_reg;
3026 }
3027
3028 //*----------------------------------------------------------------------------
3029 //* \fn    AT91F_EnableCAN()
3030 //* \brief
3031 //*----------------------------------------------------------------------------
3032 __inline void AT91F_EnableCAN(
3033         AT91PS_CAN pCAN)     // pointer to a CAN controller
3034 {
3035         pCAN->CAN_MR |= AT91C_CAN_CANEN;
3036
3037         // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver
3038         while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP );
3039 }
3040
3041 //*----------------------------------------------------------------------------
3042 //* \fn    AT91F_DisableCAN()
3043 //* \brief
3044 //*----------------------------------------------------------------------------
3045 __inline void AT91F_DisableCAN(
3046         AT91PS_CAN pCAN)     // pointer to a CAN controller
3047 {
3048         pCAN->CAN_MR &= ~AT91C_CAN_CANEN;
3049 }
3050
3051 //*----------------------------------------------------------------------------
3052 //* \fn    AT91F_CAN_EnableIt
3053 //* \brief Enable CAN interrupt
3054 //*----------------------------------------------------------------------------
3055 __inline void AT91F_CAN_EnableIt (
3056         AT91PS_CAN pCAN,     // pointer to a CAN controller
3057         unsigned int flag)   // IT to be enabled
3058 {
3059         //* Write to the IER register
3060         pCAN->CAN_IER = flag;
3061 }
3062
3063 //*----------------------------------------------------------------------------
3064 //* \fn    AT91F_CAN_DisableIt
3065 //* \brief Disable CAN interrupt
3066 //*----------------------------------------------------------------------------
3067 __inline void AT91F_CAN_DisableIt (
3068         AT91PS_CAN pCAN, // pointer to a CAN controller
3069         unsigned int flag) // IT to be disabled
3070 {
3071         //* Write to the IDR register
3072         pCAN->CAN_IDR = flag;
3073 }
3074
3075 //*----------------------------------------------------------------------------
3076 //* \fn    AT91F_CAN_GetStatus
3077 //* \brief Return CAN Interrupt Status
3078 //*----------------------------------------------------------------------------
3079 __inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status
3080         AT91PS_CAN pCAN) // pointer to a CAN controller
3081 {
3082         return pCAN->CAN_SR;
3083 }
3084
3085 //*----------------------------------------------------------------------------
3086 //* \fn    AT91F_CAN_GetInterruptMaskStatus
3087 //* \brief Return CAN Interrupt Mask Status
3088 //*----------------------------------------------------------------------------
3089 __inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status
3090         AT91PS_CAN pCAN) // pointer to a CAN controller
3091 {
3092         return pCAN->CAN_IMR;
3093 }
3094
3095 //*----------------------------------------------------------------------------
3096 //* \fn    AT91F_CAN_IsInterruptMasked
3097 //* \brief Test if CAN Interrupt is Masked
3098 //*----------------------------------------------------------------------------
3099 __inline unsigned int AT91F_CAN_IsInterruptMasked(
3100         AT91PS_CAN pCAN,   // \arg  pointer to a CAN controller
3101         unsigned int flag) // \arg  flag to be tested
3102 {
3103         return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag);
3104 }
3105
3106 //*----------------------------------------------------------------------------
3107 //* \fn    AT91F_CAN_IsStatusSet
3108 //* \brief Test if CAN Interrupt is Set
3109 //*----------------------------------------------------------------------------
3110 __inline unsigned int AT91F_CAN_IsStatusSet(
3111         AT91PS_CAN pCAN,   // \arg  pointer to a CAN controller
3112         unsigned int flag) // \arg  flag to be tested
3113 {
3114         return (AT91F_CAN_GetStatus(pCAN) & flag);
3115 }
3116
3117 //*----------------------------------------------------------------------------
3118 //* \fn    AT91F_CAN_CfgModeReg
3119 //* \brief Configure the Mode Register of the CAN controller
3120 //*----------------------------------------------------------------------------
3121 __inline void AT91F_CAN_CfgModeReg (
3122         AT91PS_CAN pCAN, // pointer to a CAN controller
3123         unsigned int mode)        // mode register
3124 {
3125         //* Write to the MR register
3126         pCAN->CAN_MR = mode;
3127 }
3128
3129 //*----------------------------------------------------------------------------
3130 //* \fn    AT91F_CAN_GetModeReg
3131 //* \brief Return the Mode Register of the CAN controller value
3132 //*----------------------------------------------------------------------------
3133 __inline unsigned int AT91F_CAN_GetModeReg (
3134         AT91PS_CAN pCAN // pointer to a CAN controller
3135         )
3136 {
3137         return pCAN->CAN_MR;
3138 }
3139
3140 //*----------------------------------------------------------------------------
3141 //* \fn    AT91F_CAN_CfgBaudrateReg
3142 //* \brief Configure the Baudrate of the CAN controller for the network
3143 //*----------------------------------------------------------------------------
3144 __inline void AT91F_CAN_CfgBaudrateReg (
3145         AT91PS_CAN pCAN, // pointer to a CAN controller
3146         unsigned int baudrate_cfg)
3147 {
3148         //* Write to the BR register
3149         pCAN->CAN_BR = baudrate_cfg;
3150 }
3151
3152 //*----------------------------------------------------------------------------
3153 //* \fn    AT91F_CAN_GetBaudrate
3154 //* \brief Return the Baudrate of the CAN controller for the network value
3155 //*----------------------------------------------------------------------------
3156 __inline unsigned int AT91F_CAN_GetBaudrate (
3157         AT91PS_CAN pCAN // pointer to a CAN controller
3158         )
3159 {
3160         return pCAN->CAN_BR;
3161 }
3162
3163 //*----------------------------------------------------------------------------
3164 //* \fn    AT91F_CAN_GetInternalCounter
3165 //* \brief Return CAN Timer Regsiter Value
3166 //*----------------------------------------------------------------------------
3167 __inline unsigned int AT91F_CAN_GetInternalCounter (
3168         AT91PS_CAN pCAN // pointer to a CAN controller
3169         )
3170 {
3171         return pCAN->CAN_TIM;
3172 }
3173
3174 //*----------------------------------------------------------------------------
3175 //* \fn    AT91F_CAN_GetTimestamp
3176 //* \brief Return CAN Timestamp Register Value
3177 //*----------------------------------------------------------------------------
3178 __inline unsigned int AT91F_CAN_GetTimestamp (
3179         AT91PS_CAN pCAN // pointer to a CAN controller
3180         )
3181 {
3182         return pCAN->CAN_TIMESTP;
3183 }
3184
3185 //*----------------------------------------------------------------------------
3186 //* \fn    AT91F_CAN_GetErrorCounter
3187 //* \brief Return CAN Error Counter Register Value
3188 //*----------------------------------------------------------------------------
3189 __inline unsigned int AT91F_CAN_GetErrorCounter (
3190         AT91PS_CAN pCAN // pointer to a CAN controller
3191         )
3192 {
3193         return pCAN->CAN_ECR;
3194 }
3195
3196 //*----------------------------------------------------------------------------
3197 //* \fn    AT91F_CAN_InitTransferRequest
3198 //* \brief Request for a transfer on the corresponding mailboxes
3199 //*----------------------------------------------------------------------------
3200 __inline void AT91F_CAN_InitTransferRequest (
3201         AT91PS_CAN pCAN, // pointer to a CAN controller
3202     unsigned int transfer_cmd)
3203 {
3204         pCAN->CAN_TCR = transfer_cmd;
3205 }
3206
3207 //*----------------------------------------------------------------------------
3208 //* \fn    AT91F_CAN_InitAbortRequest
3209 //* \brief Abort the corresponding mailboxes
3210 //*----------------------------------------------------------------------------
3211 __inline void AT91F_CAN_InitAbortRequest (
3212         AT91PS_CAN pCAN, // pointer to a CAN controller
3213     unsigned int abort_cmd)
3214 {
3215         pCAN->CAN_ACR = abort_cmd;
3216 }
3217
3218 //*----------------------------------------------------------------------------
3219 //* \fn    AT91F_CAN_CfgMessageModeReg
3220 //* \brief Program the Message Mode Register
3221 //*----------------------------------------------------------------------------
3222 __inline void AT91F_CAN_CfgMessageModeReg (
3223         AT91PS_CAN_MB   CAN_Mailbox, // pointer to a CAN Mailbox
3224     unsigned int mode)
3225 {
3226         CAN_Mailbox->CAN_MB_MMR = mode;
3227 }
3228
3229 //*----------------------------------------------------------------------------
3230 //* \fn    AT91F_CAN_GetMessageModeReg
3231 //* \brief Return the Message Mode Register
3232 //*----------------------------------------------------------------------------
3233 __inline unsigned int AT91F_CAN_GetMessageModeReg (
3234         AT91PS_CAN_MB   CAN_Mailbox) // pointer to a CAN Mailbox
3235 {
3236         return CAN_Mailbox->CAN_MB_MMR;
3237 }
3238
3239 //*----------------------------------------------------------------------------
3240 //* \fn    AT91F_CAN_CfgMessageIDReg
3241 //* \brief Program the Message ID Register
3242 //* \brief Version == 0 for Standard messsage, Version == 1 for Extended
3243 //*----------------------------------------------------------------------------
3244 __inline void AT91F_CAN_CfgMessageIDReg (
3245         AT91PS_CAN_MB   CAN_Mailbox, // pointer to a CAN Mailbox
3246     unsigned int id,
3247     unsigned char version)
3248 {
3249         if(version==0)  // IDvA Standard Format
3250                 CAN_Mailbox->CAN_MB_MID = id<<18;
3251         else    // IDvB Extended Format
3252                 CAN_Mailbox->CAN_MB_MID = id | (1<<29); // set MIDE bit
3253 }
3254
3255 //*----------------------------------------------------------------------------
3256 //* \fn    AT91F_CAN_GetMessageIDReg
3257 //* \brief Return the Message ID Register
3258 //*----------------------------------------------------------------------------
3259 __inline unsigned int AT91F_CAN_GetMessageIDReg (
3260         AT91PS_CAN_MB   CAN_Mailbox) // pointer to a CAN Mailbox
3261 {
3262         return CAN_Mailbox->CAN_MB_MID;
3263 }
3264
3265 //*----------------------------------------------------------------------------
3266 //* \fn    AT91F_CAN_CfgMessageAcceptanceMaskReg
3267 //* \brief Program the Message Acceptance Mask Register
3268 //*----------------------------------------------------------------------------
3269 __inline void AT91F_CAN_CfgMessageAcceptanceMaskReg (
3270         AT91PS_CAN_MB   CAN_Mailbox, // pointer to a CAN Mailbox
3271     unsigned int mask)
3272 {
3273         CAN_Mailbox->CAN_MB_MAM = mask;
3274 }
3275
3276 //*----------------------------------------------------------------------------
3277 //* \fn    AT91F_CAN_GetMessageAcceptanceMaskReg
3278 //* \brief Return the Message Acceptance Mask Register
3279 //*----------------------------------------------------------------------------
3280 __inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg (
3281         AT91PS_CAN_MB   CAN_Mailbox) // pointer to a CAN Mailbox
3282 {
3283         return CAN_Mailbox->CAN_MB_MAM;
3284 }
3285
3286 //*----------------------------------------------------------------------------
3287 //* \fn    AT91F_CAN_GetFamilyID
3288 //* \brief Return the Message ID Register
3289 //*----------------------------------------------------------------------------
3290 __inline unsigned int AT91F_CAN_GetFamilyID (
3291         AT91PS_CAN_MB   CAN_Mailbox) // pointer to a CAN Mailbox
3292 {
3293         return CAN_Mailbox->CAN_MB_MFID;
3294 }
3295
3296 //*----------------------------------------------------------------------------
3297 //* \fn    AT91F_CAN_CfgMessageCtrl
3298 //* \brief Request and config for a transfer on the corresponding mailbox
3299 //*----------------------------------------------------------------------------
3300 __inline void AT91F_CAN_CfgMessageCtrlReg (
3301         AT91PS_CAN_MB   CAN_Mailbox, // pointer to a CAN Mailbox
3302     unsigned int message_ctrl_cmd)
3303 {
3304         CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd;
3305 }
3306
3307 //*----------------------------------------------------------------------------
3308 //* \fn    AT91F_CAN_GetMessageStatus
3309 //* \brief Return CAN Mailbox Status
3310 //*----------------------------------------------------------------------------
3311 __inline unsigned int AT91F_CAN_GetMessageStatus (
3312         AT91PS_CAN_MB   CAN_Mailbox) // pointer to a CAN Mailbox
3313 {
3314         return CAN_Mailbox->CAN_MB_MSR;
3315 }
3316
3317 //*----------------------------------------------------------------------------
3318 //* \fn    AT91F_CAN_CfgMessageDataLow
3319 //* \brief Program data low value
3320 //*----------------------------------------------------------------------------
3321 __inline void AT91F_CAN_CfgMessageDataLow (
3322         AT91PS_CAN_MB   CAN_Mailbox, // pointer to a CAN Mailbox
3323     unsigned int data)
3324 {
3325         CAN_Mailbox->CAN_MB_MDL = data;
3326 }
3327
3328 //*----------------------------------------------------------------------------
3329 //* \fn    AT91F_CAN_GetMessageDataLow
3330 //* \brief Return data low value
3331 //*----------------------------------------------------------------------------
3332 __inline unsigned int AT91F_CAN_GetMessageDataLow (
3333         AT91PS_CAN_MB   CAN_Mailbox) // pointer to a CAN Mailbox
3334 {
3335         return CAN_Mailbox->CAN_MB_MDL;
3336 }
3337
3338 //*----------------------------------------------------------------------------
3339 //* \fn    AT91F_CAN_CfgMessageDataHigh
3340 //* \brief Program data high value
3341 //*----------------------------------------------------------------------------
3342 __inline void AT91F_CAN_CfgMessageDataHigh (
3343         AT91PS_CAN_MB   CAN_Mailbox, // pointer to a CAN Mailbox
3344     unsigned int data)
3345 {
3346         CAN_Mailbox->CAN_MB_MDH = data;
3347 }
3348
3349 //*----------------------------------------------------------------------------
3350 //* \fn    AT91F_CAN_GetMessageDataHigh
3351 //* \brief Return data high value
3352 //*----------------------------------------------------------------------------
3353 __inline unsigned int AT91F_CAN_GetMessageDataHigh (
3354         AT91PS_CAN_MB   CAN_Mailbox) // pointer to a CAN Mailbox
3355 {
3356         return CAN_Mailbox->CAN_MB_MDH;
3357 }
3358
3359 /* *****************************************************************************
3360                 SOFTWARE API FOR ADC
3361    ***************************************************************************** */
3362 //*----------------------------------------------------------------------------
3363 //* \fn    AT91F_ADC_EnableIt
3364 //* \brief Enable ADC interrupt
3365 //*----------------------------------------------------------------------------
3366 __inline void AT91F_ADC_EnableIt (
3367         AT91PS_ADC pADC,     // pointer to a ADC controller
3368         unsigned int flag)   // IT to be enabled
3369 {
3370         //* Write to the IER register
3371         pADC->ADC_IER = flag;
3372 }
3373
3374 //*----------------------------------------------------------------------------
3375 //* \fn    AT91F_ADC_DisableIt
3376 //* \brief Disable ADC interrupt
3377 //*----------------------------------------------------------------------------
3378 __inline void AT91F_ADC_DisableIt (
3379         AT91PS_ADC pADC, // pointer to a ADC controller
3380         unsigned int flag) // IT to be disabled
3381 {
3382         //* Write to the IDR register
3383         pADC->ADC_IDR = flag;
3384 }
3385
3386 //*----------------------------------------------------------------------------
3387 //* \fn    AT91F_ADC_GetStatus
3388 //* \brief Return ADC Interrupt Status
3389 //*----------------------------------------------------------------------------
3390 __inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status
3391         AT91PS_ADC pADC) // pointer to a ADC controller
3392 {
3393         return pADC->ADC_SR;
3394 }
3395
3396 //*----------------------------------------------------------------------------
3397 //* \fn    AT91F_ADC_GetInterruptMaskStatus
3398 //* \brief Return ADC Interrupt Mask Status
3399 //*----------------------------------------------------------------------------
3400 __inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status
3401         AT91PS_ADC pADC) // pointer to a ADC controller
3402 {
3403         return pADC->ADC_IMR;
3404 }
3405
3406 //*----------------------------------------------------------------------------
3407 //* \fn    AT91F_ADC_IsInterruptMasked
3408 //* \brief Test if ADC Interrupt is Masked
3409 //*----------------------------------------------------------------------------
3410 __inline unsigned int AT91F_ADC_IsInterruptMasked(
3411         AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
3412         unsigned int flag) // \arg  flag to be tested
3413 {
3414         return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag);
3415 }
3416
3417 //*----------------------------------------------------------------------------
3418 //* \fn    AT91F_ADC_IsStatusSet
3419 //* \brief Test if ADC Status is Set
3420 //*----------------------------------------------------------------------------
3421 __inline unsigned int AT91F_ADC_IsStatusSet(
3422         AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
3423         unsigned int flag) // \arg  flag to be tested
3424 {
3425         return (AT91F_ADC_GetStatus(pADC) & flag);
3426 }
3427
3428 //*----------------------------------------------------------------------------
3429 //* \fn    AT91F_ADC_CfgModeReg
3430 //* \brief Configure the Mode Register of the ADC controller
3431 //*----------------------------------------------------------------------------
3432 __inline void AT91F_ADC_CfgModeReg (
3433         AT91PS_ADC pADC, // pointer to a ADC controller
3434         unsigned int mode)        // mode register
3435 {
3436         //* Write to the MR register
3437         pADC->ADC_MR = mode;
3438 }
3439
3440 //*----------------------------------------------------------------------------
3441 //* \fn    AT91F_ADC_GetModeReg
3442 //* \brief Return the Mode Register of the ADC controller value
3443 //*----------------------------------------------------------------------------
3444 __inline unsigned int AT91F_ADC_GetModeReg (
3445         AT91PS_ADC pADC // pointer to a ADC controller
3446         )
3447 {
3448         return pADC->ADC_MR;
3449 }
3450
3451 //*----------------------------------------------------------------------------
3452 //* \fn    AT91F_ADC_CfgTimings
3453 //* \brief Configure the different necessary timings of the ADC controller
3454 //*----------------------------------------------------------------------------
3455 __inline void AT91F_ADC_CfgTimings (
3456         AT91PS_ADC pADC, // pointer to a ADC controller
3457         unsigned int mck_clock, // in MHz
3458         unsigned int adc_clock, // in MHz
3459         unsigned int startup_time, // in us
3460         unsigned int sample_and_hold_time)      // in ns
3461 {
3462         unsigned int prescal,startup,shtim;
3463
3464         prescal = mck_clock/(2*adc_clock) - 1;
3465         startup = adc_clock*startup_time/8 - 1;
3466         shtim = adc_clock*sample_and_hold_time/1000 - 1;
3467
3468         //* Write to the MR register
3469         pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);
3470 }
3471
3472 //*----------------------------------------------------------------------------
3473 //* \fn    AT91F_ADC_EnableChannel
3474 //* \brief Return ADC Timer Register Value
3475 //*----------------------------------------------------------------------------
3476 __inline void AT91F_ADC_EnableChannel (
3477         AT91PS_ADC pADC, // pointer to a ADC controller
3478         unsigned int channel)        // mode register
3479 {
3480         //* Write to the CHER register
3481         pADC->ADC_CHER = channel;
3482 }
3483
3484 //*----------------------------------------------------------------------------
3485 //* \fn    AT91F_ADC_DisableChannel
3486 //* \brief Return ADC Timer Register Value
3487 //*----------------------------------------------------------------------------
3488 __inline void AT91F_ADC_DisableChannel (
3489         AT91PS_ADC pADC, // pointer to a ADC controller
3490         unsigned int channel)        // mode register
3491 {
3492         //* Write to the CHDR register
3493         pADC->ADC_CHDR = channel;
3494 }
3495
3496 //*----------------------------------------------------------------------------
3497 //* \fn    AT91F_ADC_GetChannelStatus
3498 //* \brief Return ADC Timer Register Value
3499 //*----------------------------------------------------------------------------
3500 __inline unsigned int AT91F_ADC_GetChannelStatus (
3501         AT91PS_ADC pADC // pointer to a ADC controller
3502         )
3503 {
3504         return pADC->ADC_CHSR;
3505 }
3506
3507 //*----------------------------------------------------------------------------
3508 //* \fn    AT91F_ADC_StartConversion
3509 //* \brief Software request for a analog to digital conversion
3510 //*----------------------------------------------------------------------------
3511 __inline void AT91F_ADC_StartConversion (
3512         AT91PS_ADC pADC // pointer to a ADC controller
3513         )
3514 {
3515         pADC->ADC_CR = AT91C_ADC_START;
3516 }
3517
3518 //*----------------------------------------------------------------------------
3519 //* \fn    AT91F_ADC_SoftReset
3520 //* \brief Software reset
3521 //*----------------------------------------------------------------------------
3522 __inline void AT91F_ADC_SoftReset (
3523         AT91PS_ADC pADC // pointer to a ADC controller
3524         )
3525 {
3526         pADC->ADC_CR = AT91C_ADC_SWRST;
3527 }
3528
3529 //*----------------------------------------------------------------------------
3530 //* \fn    AT91F_ADC_GetLastConvertedData
3531 //* \brief Return the Last Converted Data
3532 //*----------------------------------------------------------------------------
3533 __inline unsigned int AT91F_ADC_GetLastConvertedData (
3534         AT91PS_ADC pADC // pointer to a ADC controller
3535         )
3536 {
3537         return pADC->ADC_LCDR;
3538 }
3539
3540 //*----------------------------------------------------------------------------
3541 //* \fn    AT91F_ADC_GetConvertedDataCH0
3542 //* \brief Return the Channel 0 Converted Data
3543 //*----------------------------------------------------------------------------
3544 __inline unsigned int AT91F_ADC_GetConvertedDataCH0 (
3545         AT91PS_ADC pADC // pointer to a ADC controller
3546         )
3547 {
3548         return pADC->ADC_CDR0;
3549 }
3550
3551 //*----------------------------------------------------------------------------
3552 //* \fn    AT91F_ADC_GetConvertedDataCH1
3553 //* \brief Return the Channel 1 Converted Data
3554 //*----------------------------------------------------------------------------
3555 __inline unsigned int AT91F_ADC_GetConvertedDataCH1 (
3556         AT91PS_ADC pADC // pointer to a ADC controller
3557         )
3558 {
3559         return pADC->ADC_CDR1;
3560 }
3561
3562 //*----------------------------------------------------------------------------
3563 //* \fn    AT91F_ADC_GetConvertedDataCH2
3564 //* \brief Return the Channel 2 Converted Data
3565 //*----------------------------------------------------------------------------
3566 __inline unsigned int AT91F_ADC_GetConvertedDataCH2 (
3567         AT91PS_ADC pADC // pointer to a ADC controller
3568         )
3569 {
3570         return pADC->ADC_CDR2;
3571 }
3572
3573 //*----------------------------------------------------------------------------
3574 //* \fn    AT91F_ADC_GetConvertedDataCH3
3575 //* \brief Return the Channel 3 Converted Data
3576 //*----------------------------------------------------------------------------
3577 __inline unsigned int AT91F_ADC_GetConvertedDataCH3 (
3578         AT91PS_ADC pADC // pointer to a ADC controller
3579         )
3580 {
3581         return pADC->ADC_CDR3;
3582 }
3583
3584 //*----------------------------------------------------------------------------
3585 //* \fn    AT91F_ADC_GetConvertedDataCH4
3586 //* \brief Return the Channel 4 Converted Data
3587 //*----------------------------------------------------------------------------
3588 __inline unsigned int AT91F_ADC_GetConvertedDataCH4 (
3589         AT91PS_ADC pADC // pointer to a ADC controller
3590         )
3591 {
3592         return pADC->ADC_CDR4;
3593 }
3594
3595 //*----------------------------------------------------------------------------
3596 //* \fn    AT91F_ADC_GetConvertedDataCH5
3597 //* \brief Return the Channel 5 Converted Data
3598 //*----------------------------------------------------------------------------
3599 __inline unsigned int AT91F_ADC_GetConvertedDataCH5 (
3600         AT91PS_ADC pADC // pointer to a ADC controller
3601         )
3602 {
3603         return pADC->ADC_CDR5;
3604 }
3605
3606 //*----------------------------------------------------------------------------
3607 //* \fn    AT91F_ADC_GetConvertedDataCH6
3608 //* \brief Return the Channel 6 Converted Data
3609 //*----------------------------------------------------------------------------
3610 __inline unsigned int AT91F_ADC_GetConvertedDataCH6 (
3611         AT91PS_ADC pADC // pointer to a ADC controller
3612         )
3613 {
3614         return pADC->ADC_CDR6;
3615 }
3616
3617 //*----------------------------------------------------------------------------
3618 //* \fn    AT91F_ADC_GetConvertedDataCH7
3619 //* \brief Return the Channel 7 Converted Data
3620 //*----------------------------------------------------------------------------
3621 __inline unsigned int AT91F_ADC_GetConvertedDataCH7 (
3622         AT91PS_ADC pADC // pointer to a ADC controller
3623         )
3624 {
3625         return pADC->ADC_CDR7;
3626 }
3627
3628 /* *****************************************************************************
3629                 SOFTWARE API FOR AES
3630    ***************************************************************************** */
3631 //*----------------------------------------------------------------------------
3632 //* \fn    AT91F_AES_EnableIt
3633 //* \brief Enable AES interrupt
3634 //*----------------------------------------------------------------------------
3635 __inline void AT91F_AES_EnableIt (
3636         AT91PS_AES pAES,     // pointer to a AES controller
3637         unsigned int flag)   // IT to be enabled
3638 {
3639         //* Write to the IER register
3640         pAES->AES_IER = flag;
3641 }
3642
3643 //*----------------------------------------------------------------------------
3644 //* \fn    AT91F_AES_DisableIt
3645 //* \brief Disable AES interrupt
3646 //*----------------------------------------------------------------------------
3647 __inline void AT91F_AES_DisableIt (
3648         AT91PS_AES pAES, // pointer to a AES controller
3649         unsigned int flag) // IT to be disabled
3650 {
3651         //* Write to the IDR register
3652         pAES->AES_IDR = flag;
3653 }
3654
3655 //*----------------------------------------------------------------------------
3656 //* \fn    AT91F_AES_GetStatus
3657 //* \brief Return AES Interrupt Status
3658 //*----------------------------------------------------------------------------
3659 __inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status
3660         AT91PS_AES pAES) // pointer to a AES controller
3661 {
3662         return pAES->AES_ISR;
3663 }
3664
3665 //*----------------------------------------------------------------------------
3666 //* \fn    AT91F_AES_GetInterruptMaskStatus
3667 //* \brief Return AES Interrupt Mask Status
3668 //*----------------------------------------------------------------------------
3669 __inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status
3670         AT91PS_AES pAES) // pointer to a AES controller
3671 {
3672         return pAES->AES_IMR;
3673 }
3674
3675 //*----------------------------------------------------------------------------
3676 //* \fn    AT91F_AES_IsInterruptMasked
3677 //* \brief Test if AES Interrupt is Masked
3678 //*----------------------------------------------------------------------------
3679 __inline unsigned int AT91F_AES_IsInterruptMasked(
3680         AT91PS_AES pAES,   // \arg  pointer to a AES controller
3681         unsigned int flag) // \arg  flag to be tested
3682 {
3683         return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag);
3684 }
3685
3686 //*----------------------------------------------------------------------------
3687 //* \fn    AT91F_AES_IsStatusSet
3688 //* \brief Test if AES Status is Set
3689 //*----------------------------------------------------------------------------
3690 __inline unsigned int AT91F_AES_IsStatusSet(
3691         AT91PS_AES pAES,   // \arg  pointer to a AES controller
3692         unsigned int flag) // \arg  flag to be tested
3693 {
3694         return (AT91F_AES_GetStatus(pAES) & flag);
3695 }
3696
3697 //*----------------------------------------------------------------------------
3698 //* \fn    AT91F_AES_CfgModeReg
3699 //* \brief Configure the Mode Register of the AES controller
3700 //*----------------------------------------------------------------------------
3701 __inline void AT91F_AES_CfgModeReg (
3702         AT91PS_AES pAES, // pointer to a AES controller
3703         unsigned int mode)        // mode register
3704 {
3705         //* Write to the MR register
3706         pAES->AES_MR = mode;
3707 }
3708
3709 //*----------------------------------------------------------------------------
3710 //* \fn    AT91F_AES_GetModeReg
3711 //* \brief Return the Mode Register of the AES controller value
3712 //*----------------------------------------------------------------------------
3713 __inline unsigned int AT91F_AES_GetModeReg (
3714         AT91PS_AES pAES // pointer to a AES controller
3715         )
3716 {
3717         return pAES->AES_MR;
3718 }
3719
3720 //*----------------------------------------------------------------------------
3721 //* \fn    AT91F_AES_StartProcessing
3722 //* \brief Start Encryption or Decryption
3723 //*----------------------------------------------------------------------------
3724 __inline void AT91F_AES_StartProcessing (
3725         AT91PS_AES pAES // pointer to a AES controller
3726         )
3727 {
3728         pAES->AES_CR = AT91C_AES_START;
3729 }
3730
3731 //*----------------------------------------------------------------------------
3732 //* \fn    AT91F_AES_SoftReset
3733 //* \brief Reset AES
3734 //*----------------------------------------------------------------------------
3735 __inline void AT91F_AES_SoftReset (
3736         AT91PS_AES pAES // pointer to a AES controller
3737         )
3738 {
3739         pAES->AES_CR = AT91C_AES_SWRST;
3740 }
3741
3742 //*----------------------------------------------------------------------------
3743 //* \fn    AT91F_AES_LoadNewSeed
3744 //* \brief Load New Seed in the random number generator
3745 //*----------------------------------------------------------------------------
3746 __inline void AT91F_AES_LoadNewSeed (
3747         AT91PS_AES pAES // pointer to a AES controller
3748         )
3749 {
3750         pAES->AES_CR = AT91C_AES_LOADSEED;
3751 }
3752
3753 //*----------------------------------------------------------------------------
3754 //* \fn    AT91F_AES_SetCryptoKey
3755 //* \brief Set Cryptographic Key x
3756 //*----------------------------------------------------------------------------
3757 __inline void AT91F_AES_SetCryptoKey (
3758         AT91PS_AES pAES, // pointer to a AES controller
3759         unsigned char index,
3760         unsigned int keyword
3761         )
3762 {
3763         pAES->AES_KEYWxR[index] = keyword;
3764 }
3765
3766 //*----------------------------------------------------------------------------
3767 //* \fn    AT91F_AES_InputData
3768 //* \brief Set Input Data x
3769 //*----------------------------------------------------------------------------
3770 __inline void AT91F_AES_InputData (
3771         AT91PS_AES pAES, // pointer to a AES controller
3772         unsigned char index,
3773         unsigned int indata
3774         )
3775 {
3776         pAES->AES_IDATAxR[index] = indata;
3777 }
3778
3779 //*----------------------------------------------------------------------------
3780 //* \fn    AT91F_AES_GetOutputData
3781 //* \brief Get Output Data x
3782 //*----------------------------------------------------------------------------
3783 __inline unsigned int AT91F_AES_GetOutputData (
3784         AT91PS_AES pAES, // pointer to a AES controller
3785         unsigned char index
3786         )
3787 {
3788         return pAES->AES_ODATAxR[index];
3789 }
3790
3791 //*----------------------------------------------------------------------------
3792 //* \fn    AT91F_AES_SetInitializationVector
3793 //* \brief Set Initialization Vector (or Counter) x
3794 //*----------------------------------------------------------------------------
3795 __inline void AT91F_AES_SetInitializationVector (
3796         AT91PS_AES pAES, // pointer to a AES controller
3797         unsigned char index,
3798         unsigned int initvector
3799         )
3800 {
3801         pAES->AES_IVxR[index] = initvector;
3802 }
3803
3804 /* *****************************************************************************
3805                 SOFTWARE API FOR TDES
3806    ***************************************************************************** */
3807 //*----------------------------------------------------------------------------
3808 //* \fn    AT91F_TDES_EnableIt
3809 //* \brief Enable TDES interrupt
3810 //*----------------------------------------------------------------------------
3811 __inline void AT91F_TDES_EnableIt (
3812         AT91PS_TDES pTDES,     // pointer to a TDES controller
3813         unsigned int flag)   // IT to be enabled
3814 {
3815         //* Write to the IER register
3816         pTDES->TDES_IER = flag;
3817 }
3818
3819 //*----------------------------------------------------------------------------
3820 //* \fn    AT91F_TDES_DisableIt
3821 //* \brief Disable TDES interrupt
3822 //*----------------------------------------------------------------------------
3823 __inline void AT91F_TDES_DisableIt (
3824         AT91PS_TDES pTDES, // pointer to a TDES controller
3825         unsigned int flag) // IT to be disabled
3826 {
3827         //* Write to the IDR register
3828         pTDES->TDES_IDR = flag;
3829 }
3830
3831 //*----------------------------------------------------------------------------
3832 //* \fn    AT91F_TDES_GetStatus
3833 //* \brief Return TDES Interrupt Status
3834 //*----------------------------------------------------------------------------
3835 __inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status
3836         AT91PS_TDES pTDES) // pointer to a TDES controller
3837 {
3838         return pTDES->TDES_ISR;
3839 }
3840
3841 //*----------------------------------------------------------------------------
3842 //* \fn    AT91F_TDES_GetInterruptMaskStatus
3843 //* \brief Return TDES Interrupt Mask Status
3844 //*----------------------------------------------------------------------------
3845 __inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status
3846         AT91PS_TDES pTDES) // pointer to a TDES controller
3847 {
3848         return pTDES->TDES_IMR;
3849 }
3850
3851 //*----------------------------------------------------------------------------
3852 //* \fn    AT91F_TDES_IsInterruptMasked
3853 //* \brief Test if TDES Interrupt is Masked
3854 //*----------------------------------------------------------------------------
3855 __inline unsigned int AT91F_TDES_IsInterruptMasked(
3856         AT91PS_TDES pTDES,   // \arg  pointer to a TDES controller
3857         unsigned int flag) // \arg  flag to be tested
3858 {
3859         return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag);
3860 }
3861
3862 //*----------------------------------------------------------------------------
3863 //* \fn    AT91F_TDES_IsStatusSet
3864 //* \brief Test if TDES Status is Set
3865 //*----------------------------------------------------------------------------
3866 __inline unsigned int AT91F_TDES_IsStatusSet(
3867         AT91PS_TDES pTDES,   // \arg  pointer to a TDES controller
3868         unsigned int flag) // \arg  flag to be tested
3869 {
3870         return (AT91F_TDES_GetStatus(pTDES) & flag);
3871 }
3872
3873 //*----------------------------------------------------------------------------
3874 //* \fn    AT91F_TDES_CfgModeReg
3875 //* \brief Configure the Mode Register of the TDES controller
3876 //*----------------------------------------------------------------------------
3877 __inline void AT91F_TDES_CfgModeReg (
3878         AT91PS_TDES pTDES, // pointer to a TDES controller
3879         unsigned int mode)        // mode register
3880 {
3881         //* Write to the MR register
3882         pTDES->TDES_MR = mode;
3883 }
3884
3885 //*----------------------------------------------------------------------------
3886 //* \fn    AT91F_TDES_GetModeReg
3887 //* \brief Return the Mode Register of the TDES controller value
3888 //*----------------------------------------------------------------------------
3889 __inline unsigned int AT91F_TDES_GetModeReg (
3890         AT91PS_TDES pTDES // pointer to a TDES controller
3891         )
3892 {
3893         return pTDES->TDES_MR;
3894 }
3895
3896 //*----------------------------------------------------------------------------
3897 //* \fn    AT91F_TDES_StartProcessing
3898 //* \brief Start Encryption or Decryption
3899 //*----------------------------------------------------------------------------
3900 __inline void AT91F_TDES_StartProcessing (
3901         AT91PS_TDES pTDES // pointer to a TDES controller
3902         )
3903 {
3904         pTDES->TDES_CR = AT91C_TDES_START;
3905 }
3906
3907 //*----------------------------------------------------------------------------
3908 //* \fn    AT91F_TDES_SoftReset
3909 //* \brief Reset TDES
3910 //*----------------------------------------------------------------------------
3911 __inline void AT91F_TDES_SoftReset (
3912         AT91PS_TDES pTDES // pointer to a TDES controller
3913         )
3914 {
3915         pTDES->TDES_CR = AT91C_TDES_SWRST;
3916 }
3917
3918 //*----------------------------------------------------------------------------
3919 //* \fn    AT91F_TDES_SetCryptoKey1
3920 //* \brief Set Cryptographic Key 1 Word x
3921 //*----------------------------------------------------------------------------
3922 __inline void AT91F_TDES_SetCryptoKey1 (
3923         AT91PS_TDES pTDES, // pointer to a TDES controller
3924         unsigned char index,
3925         unsigned int keyword
3926         )
3927 {
3928         pTDES->TDES_KEY1WxR[index] = keyword;
3929 }
3930
3931 //*----------------------------------------------------------------------------
3932 //* \fn    AT91F_TDES_SetCryptoKey2
3933 //* \brief Set Cryptographic Key 2 Word x
3934 //*----------------------------------------------------------------------------
3935 __inline void AT91F_TDES_SetCryptoKey2 (
3936         AT91PS_TDES pTDES, // pointer to a TDES controller
3937         unsigned char index,
3938         unsigned int keyword
3939         )
3940 {
3941         pTDES->TDES_KEY2WxR[index] = keyword;
3942 }
3943
3944 //*----------------------------------------------------------------------------
3945 //* \fn    AT91F_TDES_SetCryptoKey3
3946 //* \brief Set Cryptographic Key 3 Word x
3947 //*----------------------------------------------------------------------------
3948 __inline void AT91F_TDES_SetCryptoKey3 (
3949         AT91PS_TDES pTDES, // pointer to a TDES controller
3950         unsigned char index,
3951         unsigned int keyword
3952         )
3953 {
3954         pTDES->TDES_KEY3WxR[index] = keyword;
3955 }
3956
3957 //*----------------------------------------------------------------------------
3958 //* \fn    AT91F_TDES_InputData
3959 //* \brief Set Input Data x
3960 //*----------------------------------------------------------------------------
3961 __inline void AT91F_TDES_InputData (
3962         AT91PS_TDES pTDES, // pointer to a TDES controller
3963         unsigned char index,
3964         unsigned int indata
3965         )
3966 {
3967         pTDES->TDES_IDATAxR[index] = indata;
3968 }
3969
3970 //*----------------------------------------------------------------------------
3971 //* \fn    AT91F_TDES_GetOutputData
3972 //* \brief Get Output Data x
3973 //*----------------------------------------------------------------------------
3974 __inline unsigned int AT91F_TDES_GetOutputData (
3975         AT91PS_TDES pTDES, // pointer to a TDES controller
3976         unsigned char index
3977         )
3978 {
3979         return pTDES->TDES_ODATAxR[index];
3980 }
3981
3982 //*----------------------------------------------------------------------------
3983 //* \fn    AT91F_TDES_SetInitializationVector
3984 //* \brief Set Initialization Vector x
3985 //*----------------------------------------------------------------------------
3986 __inline void AT91F_TDES_SetInitializationVector (
3987         AT91PS_TDES pTDES, // pointer to a TDES controller
3988         unsigned char index,
3989         unsigned int initvector
3990         )
3991 {
3992         pTDES->TDES_IVxR[index] = initvector;
3993 }
3994
3995 //*----------------------------------------------------------------------------
3996 //* \fn    AT91F_DBGU_CfgPMC
3997 //* \brief Enable Peripheral clock in PMC for  DBGU
3998 //*----------------------------------------------------------------------------
3999 __inline void AT91F_DBGU_CfgPMC (void)
4000 {
4001         AT91F_PMC_EnablePeriphClock(
4002                 AT91C_BASE_PMC, // PIO controller base address
4003                 ((unsigned int) 1 << AT91C_ID_SYS));
4004 }
4005
4006 //*----------------------------------------------------------------------------
4007 //* \fn    AT91F_DBGU_CfgPIO
4008 //* \brief Configure PIO controllers to drive DBGU signals
4009 //*----------------------------------------------------------------------------
4010 __inline void AT91F_DBGU_CfgPIO (void)
4011 {
4012         // Configure PIO controllers to periph mode
4013         AT91F_PIO_CfgPeriph(
4014                 AT91C_BASE_PIOA, // PIO controller base address
4015                 ((unsigned int) AT91C_PA27_DRXD    ) |
4016                 ((unsigned int) AT91C_PA28_DTXD    ), // Peripheral A
4017                 0); // Peripheral B
4018 }
4019
4020 //*----------------------------------------------------------------------------
4021 //* \fn    AT91F_PMC_CfgPMC
4022 //* \brief Enable Peripheral clock in PMC for  PMC
4023 //*----------------------------------------------------------------------------
4024 __inline void AT91F_PMC_CfgPMC (void)
4025 {
4026         AT91F_PMC_EnablePeriphClock(
4027                 AT91C_BASE_PMC, // PIO controller base address
4028                 ((unsigned int) 1 << AT91C_ID_SYS));
4029 }
4030
4031 //*----------------------------------------------------------------------------
4032 //* \fn    AT91F_PMC_CfgPIO
4033 //* \brief Configure PIO controllers to drive PMC signals
4034 //*----------------------------------------------------------------------------
4035 __inline void AT91F_PMC_CfgPIO (void)
4036 {
4037         // Configure PIO controllers to periph mode
4038         AT91F_PIO_CfgPeriph(
4039                 AT91C_BASE_PIOB, // PIO controller base address
4040                 ((unsigned int) AT91C_PB30_PCK2    ) |
4041                 ((unsigned int) AT91C_PB29_PCK1    ), // Peripheral A
4042                 ((unsigned int) AT91C_PB20_PCK0    ) |
4043                 ((unsigned int) AT91C_PB0_PCK0    ) |
4044                 ((unsigned int) AT91C_PB22_PCK2    ) |
4045                 ((unsigned int) AT91C_PB21_PCK1    )); // Peripheral B
4046         // Configure PIO controllers to periph mode
4047         AT91F_PIO_CfgPeriph(
4048                 AT91C_BASE_PIOA, // PIO controller base address
4049                 0, // Peripheral A
4050                 ((unsigned int) AT91C_PA30_PCK2    ) |
4051                 ((unsigned int) AT91C_PA13_PCK1    ) |
4052                 ((unsigned int) AT91C_PA27_PCK3    )); // Peripheral B
4053 }
4054
4055 //*----------------------------------------------------------------------------
4056 //* \fn    AT91F_VREG_CfgPMC
4057 //* \brief Enable Peripheral clock in PMC for  VREG
4058 //*----------------------------------------------------------------------------
4059 __inline void AT91F_VREG_CfgPMC (void)
4060 {
4061         AT91F_PMC_EnablePeriphClock(
4062                 AT91C_BASE_PMC, // PIO controller base address
4063                 ((unsigned int) 1 << AT91C_ID_SYS));
4064 }
4065
4066 //*----------------------------------------------------------------------------
4067 //* \fn    AT91F_RSTC_CfgPMC
4068 //* \brief Enable Peripheral clock in PMC for  RSTC
4069 //*----------------------------------------------------------------------------
4070 __inline void AT91F_RSTC_CfgPMC (void)
4071 {
4072         AT91F_PMC_EnablePeriphClock(
4073                 AT91C_BASE_PMC, // PIO controller base address
4074                 ((unsigned int) 1 << AT91C_ID_SYS));
4075 }
4076
4077 //*----------------------------------------------------------------------------
4078 //* \fn    AT91F_SSC_CfgPMC
4079 //* \brief Enable Peripheral clock in PMC for  SSC
4080 //*----------------------------------------------------------------------------
4081 __inline void AT91F_SSC_CfgPMC (void)
4082 {
4083         AT91F_PMC_EnablePeriphClock(
4084                 AT91C_BASE_PMC, // PIO controller base address
4085                 ((unsigned int) 1 << AT91C_ID_SSC));
4086 }
4087
4088 //*----------------------------------------------------------------------------
4089 //* \fn    AT91F_SSC_CfgPIO
4090 //* \brief Configure PIO controllers to drive SSC signals
4091 //*----------------------------------------------------------------------------
4092 __inline void AT91F_SSC_CfgPIO (void)
4093 {
4094         // Configure PIO controllers to periph mode
4095         AT91F_PIO_CfgPeriph(
4096                 AT91C_BASE_PIOA, // PIO controller base address
4097                 ((unsigned int) AT91C_PA25_RK      ) |
4098                 ((unsigned int) AT91C_PA22_TK      ) |
4099                 ((unsigned int) AT91C_PA21_TF      ) |
4100                 ((unsigned int) AT91C_PA24_RD      ) |
4101                 ((unsigned int) AT91C_PA26_RF      ) |
4102                 ((unsigned int) AT91C_PA23_TD      ), // Peripheral A
4103                 0); // Peripheral B
4104 }
4105
4106 //*----------------------------------------------------------------------------
4107 //* \fn    AT91F_WDTC_CfgPMC
4108 //* \brief Enable Peripheral clock in PMC for  WDTC
4109 //*----------------------------------------------------------------------------
4110 __inline void AT91F_WDTC_CfgPMC (void)
4111 {
4112         AT91F_PMC_EnablePeriphClock(
4113                 AT91C_BASE_PMC, // PIO controller base address
4114                 ((unsigned int) 1 << AT91C_ID_SYS));
4115 }
4116
4117 //*----------------------------------------------------------------------------
4118 //* \fn    AT91F_US1_CfgPMC
4119 //* \brief Enable Peripheral clock in PMC for  US1
4120 //*----------------------------------------------------------------------------
4121 __inline void AT91F_US1_CfgPMC (void)
4122 {
4123         AT91F_PMC_EnablePeriphClock(
4124                 AT91C_BASE_PMC, // PIO controller base address
4125                 ((unsigned int) 1 << AT91C_ID_US1));
4126 }
4127
4128 //*----------------------------------------------------------------------------
4129 //* \fn    AT91F_US1_CfgPIO
4130 //* \brief Configure PIO controllers to drive US1 signals
4131 //*----------------------------------------------------------------------------
4132 __inline void AT91F_US1_CfgPIO (void)
4133 {
4134         // Configure PIO controllers to periph mode
4135         AT91F_PIO_CfgPeriph(
4136                 AT91C_BASE_PIOB, // PIO controller base address
4137                 0, // Peripheral A
4138                 ((unsigned int) AT91C_PB26_RI1     ) |
4139                 ((unsigned int) AT91C_PB24_DSR1    ) |
4140                 ((unsigned int) AT91C_PB23_DCD1    ) |
4141                 ((unsigned int) AT91C_PB25_DTR1    )); // Peripheral B
4142         // Configure PIO controllers to periph mode
4143         AT91F_PIO_CfgPeriph(
4144                 AT91C_BASE_PIOA, // PIO controller base address
4145                 ((unsigned int) AT91C_PA7_SCK1    ) |
4146                 ((unsigned int) AT91C_PA8_RTS1    ) |
4147                 ((unsigned int) AT91C_PA6_TXD1    ) |
4148                 ((unsigned int) AT91C_PA5_RXD1    ) |
4149                 ((unsigned int) AT91C_PA9_CTS1    ), // Peripheral A
4150                 0); // Peripheral B
4151 }
4152
4153 //*----------------------------------------------------------------------------
4154 //* \fn    AT91F_US0_CfgPMC
4155 //* \brief Enable Peripheral clock in PMC for  US0
4156 //*----------------------------------------------------------------------------
4157 __inline void AT91F_US0_CfgPMC (void)
4158 {
4159         AT91F_PMC_EnablePeriphClock(
4160                 AT91C_BASE_PMC, // PIO controller base address
4161                 ((unsigned int) 1 << AT91C_ID_US0));
4162 }
4163
4164 //*----------------------------------------------------------------------------
4165 //* \fn    AT91F_US0_CfgPIO
4166 //* \brief Configure PIO controllers to drive US0 signals
4167 //*----------------------------------------------------------------------------
4168 __inline void AT91F_US0_CfgPIO (void)
4169 {
4170         // Configure PIO controllers to periph mode
4171         AT91F_PIO_CfgPeriph(
4172                 AT91C_BASE_PIOA, // PIO controller base address
4173                 ((unsigned int) AT91C_PA0_RXD0    ) |
4174                 ((unsigned int) AT91C_PA4_CTS0    ) |
4175                 ((unsigned int) AT91C_PA3_RTS0    ) |
4176                 ((unsigned int) AT91C_PA2_SCK0    ) |
4177                 ((unsigned int) AT91C_PA1_TXD0    ), // Peripheral A
4178                 0); // Peripheral B
4179 }
4180
4181 //*----------------------------------------------------------------------------
4182 //* \fn    AT91F_SPI1_CfgPMC
4183 //* \brief Enable Peripheral clock in PMC for  SPI1
4184 //*----------------------------------------------------------------------------
4185 __inline void AT91F_SPI1_CfgPMC (void)
4186 {
4187         AT91F_PMC_EnablePeriphClock(
4188                 AT91C_BASE_PMC, // PIO controller base address
4189                 ((unsigned int) 1 << AT91C_ID_SPI1));
4190 }
4191
4192 //*----------------------------------------------------------------------------
4193 //* \fn    AT91F_SPI1_CfgPIO
4194 //* \brief Configure PIO controllers to drive SPI1 signals
4195 //*----------------------------------------------------------------------------
4196 __inline void AT91F_SPI1_CfgPIO (void)
4197 {
4198         // Configure PIO controllers to periph mode
4199         AT91F_PIO_CfgPeriph(
4200                 AT91C_BASE_PIOB, // PIO controller base address
4201                 0, // Peripheral A
4202                 ((unsigned int) AT91C_PB11_SPI1_NPCS2) |
4203                 ((unsigned int) AT91C_PB10_SPI1_NPCS1) |
4204                 ((unsigned int) AT91C_PB16_SPI1_NPCS3)); // Peripheral B
4205         // Configure PIO controllers to periph mode
4206         AT91F_PIO_CfgPeriph(
4207                 AT91C_BASE_PIOA, // PIO controller base address
4208                 0, // Peripheral A
4209                 ((unsigned int) AT91C_PA22_SPI1_SPCK) |
4210                 ((unsigned int) AT91C_PA3_SPI1_NPCS2) |
4211                 ((unsigned int) AT91C_PA26_SPI1_NPCS2) |
4212                 ((unsigned int) AT91C_PA25_SPI1_NPCS1) |
4213                 ((unsigned int) AT91C_PA2_SPI1_NPCS1) |
4214                 ((unsigned int) AT91C_PA24_SPI1_MISO) |
4215                 ((unsigned int) AT91C_PA4_SPI1_NPCS3) |
4216                 ((unsigned int) AT91C_PA29_SPI1_NPCS3) |
4217                 ((unsigned int) AT91C_PA21_SPI1_NPCS0) |
4218                 ((unsigned int) AT91C_PA23_SPI1_MOSI)); // Peripheral B
4219 }
4220
4221 //*----------------------------------------------------------------------------
4222 //* \fn    AT91F_SPI0_CfgPMC
4223 //* \brief Enable Peripheral clock in PMC for  SPI0
4224 //*----------------------------------------------------------------------------
4225 __inline void AT91F_SPI0_CfgPMC (void)
4226 {
4227         AT91F_PMC_EnablePeriphClock(
4228                 AT91C_BASE_PMC, // PIO controller base address
4229                 ((unsigned int) 1 << AT91C_ID_SPI0));
4230 }
4231
4232 //*----------------------------------------------------------------------------
4233 //* \fn    AT91F_SPI0_CfgPIO
4234 //* \brief Configure PIO controllers to drive SPI0 signals
4235 //*----------------------------------------------------------------------------
4236 __inline void AT91F_SPI0_CfgPIO (void)
4237 {
4238         // Configure PIO controllers to periph mode
4239         AT91F_PIO_CfgPeriph(
4240                 AT91C_BASE_PIOB, // PIO controller base address
4241                 0, // Peripheral A
4242                 ((unsigned int) AT91C_PB13_SPI0_NPCS1) |
4243                 ((unsigned int) AT91C_PB14_SPI0_NPCS2) |
4244                 ((unsigned int) AT91C_PB17_SPI0_NPCS3)); // Peripheral B
4245         // Configure PIO controllers to periph mode
4246         AT91F_PIO_CfgPeriph(
4247                 AT91C_BASE_PIOA, // PIO controller base address
4248                 ((unsigned int) AT91C_PA16_SPI0_MISO) |
4249                 ((unsigned int) AT91C_PA13_SPI0_NPCS1) |
4250                 ((unsigned int) AT91C_PA14_SPI0_NPCS2) |
4251                 ((unsigned int) AT91C_PA12_SPI0_NPCS0) |
4252                 ((unsigned int) AT91C_PA17_SPI0_MOSI) |
4253                 ((unsigned int) AT91C_PA15_SPI0_NPCS3) |
4254                 ((unsigned int) AT91C_PA18_SPI0_SPCK), // Peripheral A
4255                 ((unsigned int) AT91C_PA7_SPI0_NPCS1) |
4256                 ((unsigned int) AT91C_PA8_SPI0_NPCS2) |
4257                 ((unsigned int) AT91C_PA9_SPI0_NPCS3)); // Peripheral B
4258 }
4259
4260 //*----------------------------------------------------------------------------
4261 //* \fn    AT91F_PITC_CfgPMC
4262 //* \brief Enable Peripheral clock in PMC for  PITC
4263 //*----------------------------------------------------------------------------
4264 __inline void AT91F_PITC_CfgPMC (void)
4265 {
4266         AT91F_PMC_EnablePeriphClock(
4267                 AT91C_BASE_PMC, // PIO controller base address
4268                 ((unsigned int) 1 << AT91C_ID_SYS));
4269 }
4270
4271 //*----------------------------------------------------------------------------
4272 //* \fn    AT91F_AIC_CfgPMC
4273 //* \brief Enable Peripheral clock in PMC for  AIC
4274 //*----------------------------------------------------------------------------
4275 __inline void AT91F_AIC_CfgPMC (void)
4276 {
4277         AT91F_PMC_EnablePeriphClock(
4278                 AT91C_BASE_PMC, // PIO controller base address
4279                 ((unsigned int) 1 << AT91C_ID_FIQ) |
4280                 ((unsigned int) 1 << AT91C_ID_IRQ0) |
4281                 ((unsigned int) 1 << AT91C_ID_IRQ1));
4282 }
4283
4284 //*----------------------------------------------------------------------------
4285 //* \fn    AT91F_AIC_CfgPIO
4286 //* \brief Configure PIO controllers to drive AIC signals
4287 //*----------------------------------------------------------------------------
4288 __inline void AT91F_AIC_CfgPIO (void)
4289 {
4290         // Configure PIO controllers to periph mode
4291         AT91F_PIO_CfgPeriph(
4292                 AT91C_BASE_PIOA, // PIO controller base address
4293                 ((unsigned int) AT91C_PA30_IRQ0    ) |
4294                 ((unsigned int) AT91C_PA29_FIQ     ), // Peripheral A
4295                 ((unsigned int) AT91C_PA14_IRQ1    )); // Peripheral B
4296 }
4297
4298 //*----------------------------------------------------------------------------
4299 //* \fn    AT91F_AES_CfgPMC
4300 //* \brief Enable Peripheral clock in PMC for  AES
4301 //*----------------------------------------------------------------------------
4302 __inline void AT91F_AES_CfgPMC (void)
4303 {
4304         AT91F_PMC_EnablePeriphClock(
4305                 AT91C_BASE_PMC, // PIO controller base address
4306                 ((unsigned int) 1 << AT91C_ID_AES));
4307 }
4308
4309 //*----------------------------------------------------------------------------
4310 //* \fn    AT91F_TWI_CfgPMC
4311 //* \brief Enable Peripheral clock in PMC for  TWI
4312 //*----------------------------------------------------------------------------
4313 __inline void AT91F_TWI_CfgPMC (void)
4314 {
4315         AT91F_PMC_EnablePeriphClock(
4316                 AT91C_BASE_PMC, // PIO controller base address
4317                 ((unsigned int) 1 << AT91C_ID_TWI));
4318 }
4319
4320 //*----------------------------------------------------------------------------
4321 //* \fn    AT91F_TWI_CfgPIO
4322 //* \brief Configure PIO controllers to drive TWI signals
4323 //*----------------------------------------------------------------------------
4324 __inline void AT91F_TWI_CfgPIO (void)
4325 {
4326         // Configure PIO controllers to periph mode
4327         AT91F_PIO_CfgPeriph(
4328                 AT91C_BASE_PIOA, // PIO controller base address
4329                 ((unsigned int) AT91C_PA11_TWCK    ) |
4330                 ((unsigned int) AT91C_PA10_TWD     ), // Peripheral A
4331                 0); // Peripheral B
4332 }
4333
4334 //*----------------------------------------------------------------------------
4335 //* \fn    AT91F_ADC_CfgPMC
4336 //* \brief Enable Peripheral clock in PMC for  ADC
4337 //*----------------------------------------------------------------------------
4338 __inline void AT91F_ADC_CfgPMC (void)
4339 {
4340         AT91F_PMC_EnablePeriphClock(
4341                 AT91C_BASE_PMC, // PIO controller base address
4342                 ((unsigned int) 1 << AT91C_ID_ADC));
4343 }
4344
4345 //*----------------------------------------------------------------------------
4346 //* \fn    AT91F_ADC_CfgPIO
4347 //* \brief Configure PIO controllers to drive ADC signals
4348 //*----------------------------------------------------------------------------
4349 __inline void AT91F_ADC_CfgPIO (void)
4350 {
4351         // Configure PIO controllers to periph mode
4352         AT91F_PIO_CfgPeriph(
4353                 AT91C_BASE_PIOB, // PIO controller base address
4354                 0, // Peripheral A
4355                 ((unsigned int) AT91C_PB18_ADTRG   )); // Peripheral B
4356 }
4357
4358 //*----------------------------------------------------------------------------
4359 //* \fn    AT91F_PWMC_CH3_CfgPIO
4360 //* \brief Configure PIO controllers to drive PWMC_CH3 signals
4361 //*----------------------------------------------------------------------------
4362 __inline void AT91F_PWMC_CH3_CfgPIO (void)
4363 {
4364         // Configure PIO controllers to periph mode
4365         AT91F_PIO_CfgPeriph(
4366                 AT91C_BASE_PIOB, // PIO controller base address
4367                 ((unsigned int) AT91C_PB22_PWM3    ), // Peripheral A
4368                 ((unsigned int) AT91C_PB30_PWM3    )); // Peripheral B
4369 }
4370
4371 //*----------------------------------------------------------------------------
4372 //* \fn    AT91F_PWMC_CH2_CfgPIO
4373 //* \brief Configure PIO controllers to drive PWMC_CH2 signals
4374 //*----------------------------------------------------------------------------
4375 __inline void AT91F_PWMC_CH2_CfgPIO (void)
4376 {
4377         // Configure PIO controllers to periph mode
4378         AT91F_PIO_CfgPeriph(
4379                 AT91C_BASE_PIOB, // PIO controller base address
4380                 ((unsigned int) AT91C_PB21_PWM2    ), // Peripheral A
4381                 ((unsigned int) AT91C_PB29_PWM2    )); // Peripheral B
4382 }
4383
4384 //*----------------------------------------------------------------------------
4385 //* \fn    AT91F_PWMC_CH1_CfgPIO
4386 //* \brief Configure PIO controllers to drive PWMC_CH1 signals
4387 //*----------------------------------------------------------------------------
4388 __inline void AT91F_PWMC_CH1_CfgPIO (void)
4389 {
4390         // Configure PIO controllers to periph mode
4391         AT91F_PIO_CfgPeriph(
4392                 AT91C_BASE_PIOB, // PIO controller base address
4393                 ((unsigned int) AT91C_PB20_PWM1    ), // Peripheral A
4394                 ((unsigned int) AT91C_PB28_PWM1    )); // Peripheral B
4395 }
4396
4397 //*----------------------------------------------------------------------------
4398 //* \fn    AT91F_PWMC_CH0_CfgPIO
4399 //* \brief Configure PIO controllers to drive PWMC_CH0 signals
4400 //*----------------------------------------------------------------------------
4401 __inline void AT91F_PWMC_CH0_CfgPIO (void)
4402 {
4403         // Configure PIO controllers to periph mode
4404         AT91F_PIO_CfgPeriph(
4405                 AT91C_BASE_PIOB, // PIO controller base address
4406                 ((unsigned int) AT91C_PB19_PWM0    ), // Peripheral A
4407                 ((unsigned int) AT91C_PB27_PWM0    )); // Peripheral B
4408 }
4409
4410 //*----------------------------------------------------------------------------
4411 //* \fn    AT91F_RTTC_CfgPMC
4412 //* \brief Enable Peripheral clock in PMC for  RTTC
4413 //*----------------------------------------------------------------------------
4414 __inline void AT91F_RTTC_CfgPMC (void)
4415 {
4416         AT91F_PMC_EnablePeriphClock(
4417                 AT91C_BASE_PMC, // PIO controller base address
4418                 ((unsigned int) 1 << AT91C_ID_SYS));
4419 }
4420
4421 //*----------------------------------------------------------------------------
4422 //* \fn    AT91F_UDP_CfgPMC
4423 //* \brief Enable Peripheral clock in PMC for  UDP
4424 //*----------------------------------------------------------------------------
4425 __inline void AT91F_UDP_CfgPMC (void)
4426 {
4427         AT91F_PMC_EnablePeriphClock(
4428                 AT91C_BASE_PMC, // PIO controller base address
4429                 ((unsigned int) 1 << AT91C_ID_UDP));
4430 }
4431
4432 //*----------------------------------------------------------------------------
4433 //* \fn    AT91F_TDES_CfgPMC
4434 //* \brief Enable Peripheral clock in PMC for  TDES
4435 //*----------------------------------------------------------------------------
4436 __inline void AT91F_TDES_CfgPMC (void)
4437 {
4438         AT91F_PMC_EnablePeriphClock(
4439                 AT91C_BASE_PMC, // PIO controller base address
4440                 ((unsigned int) 1 << AT91C_ID_TDES));
4441 }
4442
4443 //*----------------------------------------------------------------------------
4444 //* \fn    AT91F_EMAC_CfgPMC
4445 //* \brief Enable Peripheral clock in PMC for  EMAC
4446 //*----------------------------------------------------------------------------
4447 __inline void AT91F_EMAC_CfgPMC (void)
4448 {
4449         AT91F_PMC_EnablePeriphClock(
4450                 AT91C_BASE_PMC, // PIO controller base address
4451                 ((unsigned int) 1 << AT91C_ID_EMAC));
4452 }
4453
4454 //*----------------------------------------------------------------------------
4455 //* \fn    AT91F_EMAC_CfgPIO
4456 //* \brief Configure PIO controllers to drive EMAC signals
4457 //*----------------------------------------------------------------------------
4458 __inline void AT91F_EMAC_CfgPIO (void)
4459 {
4460   // Configure PIO controllers to periph mode
4461   AT91F_PIO_CfgPeriph(
4462     AT91C_BASE_PIOB, // PIO controller base address
4463     ((unsigned int) AT91C_PB2_ETX0    ) |
4464 #ifdef ATMEL_EK
4465     /* M2M: On the OC8-N PB12 is not connected to the PHY */
4466     ((unsigned int) AT91C_PB12_ETXER   ) |
4467     /* M2M: PB18 Ethernet Force 100Mb only used on RMII
4468      * The EK-board has PB18 connected to the Powerdown of the DM9161 PHY. So, DON'T use peripheral mode!
4469      */
4470     //((unsigned int) AT91C_PB18_EF100   ) |
4471 #endif
4472     ((unsigned int) AT91C_PB16_ECOL    ) |
4473     ((unsigned int) AT91C_PB15_ERXDV_ECRSDV) |
4474     ((unsigned int) AT91C_PB11_ETX3    ) |
4475     ((unsigned int) AT91C_PB6_ERX1    ) |
4476     ((unsigned int) AT91C_PB13_ERX2    ) |
4477     ((unsigned int) AT91C_PB3_ETX1    ) |
4478     ((unsigned int) AT91C_PB4_ECRS    ) |
4479     ((unsigned int) AT91C_PB8_EMDC    ) |
4480     ((unsigned int) AT91C_PB5_ERX0    ) |
4481     ((unsigned int) AT91C_PB14_ERX3    ) |
4482     ((unsigned int) AT91C_PB1_ETXEN   ) |
4483     ((unsigned int) AT91C_PB10_ETX2    ) |
4484     ((unsigned int) AT91C_PB0_ETXCK_EREFCK) |
4485     ((unsigned int) AT91C_PB9_EMDIO   ) |
4486     ((unsigned int) AT91C_PB7_ERXER   ) |
4487     ((unsigned int) AT91C_PB17_ERXCK   ), // Peripheral A
4488     0); // Peripheral B
4489 }
4490
4491 //*----------------------------------------------------------------------------
4492 //* \fn    AT91F_TC0_CfgPMC
4493 //* \brief Enable Peripheral clock in PMC for  TC0
4494 //*----------------------------------------------------------------------------
4495 __inline void AT91F_TC0_CfgPMC (void)
4496 {
4497         AT91F_PMC_EnablePeriphClock(
4498                 AT91C_BASE_PMC, // PIO controller base address
4499                 ((unsigned int) 1 << AT91C_ID_TC0));
4500 }
4501
4502 //*----------------------------------------------------------------------------
4503 //* \fn    AT91F_TC0_CfgPIO
4504 //* \brief Configure PIO controllers to drive TC0 signals
4505 //*----------------------------------------------------------------------------
4506 __inline void AT91F_TC0_CfgPIO (void)
4507 {
4508         // Configure PIO controllers to periph mode
4509         AT91F_PIO_CfgPeriph(
4510                 AT91C_BASE_PIOB, // PIO controller base address
4511                 ((unsigned int) AT91C_PB23_TIOA0   ) |
4512                 ((unsigned int) AT91C_PB24_TIOB0   ), // Peripheral A
4513                 ((unsigned int) AT91C_PB12_TCLK0   )); // Peripheral B
4514 }
4515
4516 //*----------------------------------------------------------------------------
4517 //* \fn    AT91F_TC1_CfgPMC
4518 //* \brief Enable Peripheral clock in PMC for  TC1
4519 //*----------------------------------------------------------------------------
4520 __inline void AT91F_TC1_CfgPMC (void)
4521 {
4522         AT91F_PMC_EnablePeriphClock(
4523                 AT91C_BASE_PMC, // PIO controller base address
4524                 ((unsigned int) 1 << AT91C_ID_TC1));
4525 }
4526
4527 //*----------------------------------------------------------------------------
4528 //* \fn    AT91F_TC1_CfgPIO
4529 //* \brief Configure PIO controllers to drive TC1 signals
4530 //*----------------------------------------------------------------------------
4531 __inline void AT91F_TC1_CfgPIO (void)
4532 {
4533         // Configure PIO controllers to periph mode
4534         AT91F_PIO_CfgPeriph(
4535                 AT91C_BASE_PIOB, // PIO controller base address
4536                 ((unsigned int) AT91C_PB25_TIOA1   ) |
4537                 ((unsigned int) AT91C_PB26_TIOB1   ), // Peripheral A
4538                 ((unsigned int) AT91C_PB19_TCLK1   )); // Peripheral B
4539 }
4540
4541 //*----------------------------------------------------------------------------
4542 //* \fn    AT91F_TC2_CfgPMC
4543 //* \brief Enable Peripheral clock in PMC for  TC2
4544 //*----------------------------------------------------------------------------
4545 __inline void AT91F_TC2_CfgPMC (void)
4546 {
4547         AT91F_PMC_EnablePeriphClock(
4548                 AT91C_BASE_PMC, // PIO controller base address
4549                 ((unsigned int) 1 << AT91C_ID_TC2));
4550 }
4551
4552 //*----------------------------------------------------------------------------
4553 //* \fn    AT91F_TC2_CfgPIO
4554 //* \brief Configure PIO controllers to drive TC2 signals
4555 //*----------------------------------------------------------------------------
4556 __inline void AT91F_TC2_CfgPIO (void)
4557 {
4558         // Configure PIO controllers to periph mode
4559         AT91F_PIO_CfgPeriph(
4560                 AT91C_BASE_PIOB, // PIO controller base address
4561                 ((unsigned int) AT91C_PB28_TIOB2   ) |
4562                 ((unsigned int) AT91C_PB27_TIOA2   ), // Peripheral A
4563                 0); // Peripheral B
4564         // Configure PIO controllers to periph mode
4565         AT91F_PIO_CfgPeriph(
4566                 AT91C_BASE_PIOA, // PIO controller base address
4567                 0, // Peripheral A
4568                 ((unsigned int) AT91C_PA15_TCLK2   )); // Peripheral B
4569 }
4570
4571 //*----------------------------------------------------------------------------
4572 //* \fn    AT91F_MC_CfgPMC
4573 //* \brief Enable Peripheral clock in PMC for  MC
4574 //*----------------------------------------------------------------------------
4575 __inline void AT91F_MC_CfgPMC (void)
4576 {
4577         AT91F_PMC_EnablePeriphClock(
4578                 AT91C_BASE_PMC, // PIO controller base address
4579                 ((unsigned int) 1 << AT91C_ID_SYS));
4580 }
4581
4582 //*----------------------------------------------------------------------------
4583 //* \fn    AT91F_PIOA_CfgPMC
4584 //* \brief Enable Peripheral clock in PMC for  PIOA
4585 //*----------------------------------------------------------------------------
4586 __inline void AT91F_PIOA_CfgPMC (void)
4587 {
4588         AT91F_PMC_EnablePeriphClock(
4589                 AT91C_BASE_PMC, // PIO controller base address
4590                 ((unsigned int) 1 << AT91C_ID_PIOA));
4591 }
4592
4593 //*----------------------------------------------------------------------------
4594 //* \fn    AT91F_PIOB_CfgPMC
4595 //* \brief Enable Peripheral clock in PMC for  PIOB
4596 //*----------------------------------------------------------------------------
4597 __inline void AT91F_PIOB_CfgPMC (void)
4598 {
4599         AT91F_PMC_EnablePeriphClock(
4600                 AT91C_BASE_PMC, // PIO controller base address
4601                 ((unsigned int) 1 << AT91C_ID_PIOB));
4602 }
4603
4604 //*----------------------------------------------------------------------------
4605 //* \fn    AT91F_CAN_CfgPMC
4606 //* \brief Enable Peripheral clock in PMC for  CAN
4607 //*----------------------------------------------------------------------------
4608 __inline void AT91F_CAN_CfgPMC (void)
4609 {
4610         AT91F_PMC_EnablePeriphClock(
4611                 AT91C_BASE_PMC, // PIO controller base address
4612                 ((unsigned int) 1 << AT91C_ID_CAN));
4613 }
4614
4615 //*----------------------------------------------------------------------------
4616 //* \fn    AT91F_CAN_CfgPIO
4617 //* \brief Configure PIO controllers to drive CAN signals
4618 //*----------------------------------------------------------------------------
4619 __inline void AT91F_CAN_CfgPIO (void)
4620 {
4621         // Configure PIO controllers to periph mode
4622         AT91F_PIO_CfgPeriph(
4623                 AT91C_BASE_PIOA, // PIO controller base address
4624                 ((unsigned int) AT91C_PA20_CANTX   ) |
4625                 ((unsigned int) AT91C_PA19_CANRX   ), // Peripheral A
4626                 0); // Peripheral B
4627 }
4628
4629 //*----------------------------------------------------------------------------
4630 //* \fn    AT91F_PWMC_CfgPMC
4631 //* \brief Enable Peripheral clock in PMC for  PWMC
4632 //*----------------------------------------------------------------------------
4633 __inline void AT91F_PWMC_CfgPMC (void)
4634 {
4635         AT91F_PMC_EnablePeriphClock(
4636                 AT91C_BASE_PMC, // PIO controller base address
4637                 ((unsigned int) 1 << AT91C_ID_PWMC));
4638 }
4639
4640 /** @} */
4641 #endif /* lib_AT91SAM7XC256_H */