4 #include <system_def.h>
8 /*#define USE_FONT_6x8*/
11 #define HIT_LOAD_BAUD 0
19 extern char __boot_fn_start;
20 extern char __boot_fn_end;
22 void RelocatedProgMode(unsigned long where, unsigned baud)
24 void (*ProgMode_ptr)(unsigned baud);
25 unsigned long reloc_offs=where-(unsigned long)&__boot_fn_start;
26 size_t reloc_size=&__boot_fn_end-&__boot_fn_start;
27 ProgMode_ptr=&ProgMode;
28 (__u8*)ProgMode_ptr+=reloc_offs;
29 memcpy((char*)where,&__boot_fn_start,reloc_size);
30 (*ProgMode_ptr)(baud);
33 void flash_loader(void)
35 SCIInit(HIT_LOAD_BAUD);
37 if((__u8*)&__boot_fn_start<(__u8*)0xff0000)
38 RelocatedProgMode(0xffb000,HIT_LOAD_BAUD);
40 ProgMode(HIT_LOAD_BAUD);
43 inline int call_address(unsigned long addr)
45 typedef int (*my_call_t)(void);
46 my_call_t my_call=(my_call_t)addr;
52 /* Internal RAM enabled, advanced interrupt mode */
53 /* *SYS_SYSCR = 1*SYSCR_RAMEm | 1*SYSCR_INTM1m ; */
55 /* Remap 4kB of RAM from 0xffd000-0xffdfff to 0x0-0xfff */
56 /* *FLM_RAMER= 1*RAMER_RAMSm | 0&RAMER_RAMxm */
57 /* Sideefect - sets Flash software protection */
59 /* Enables access to flash control registers */
60 *IIC_SCRX |= SCRX_FLSHEm;
62 /* set shaddow registers */
66 /* Setup system clock oscilator */
68 /* *SYS_LPWRCR=2&LPWRCR_STCxm; */
70 /* *SYS_LPWRCR=1&LPWRCR_STCxm; */
71 { const char clkrat2stc[]={0,0/*1*/,1/*2*/,1,2/*4*/,2,2,2,3/*8*/};
72 *SYS_LPWRCR=LPWRCR_STCxm&(LPWRCR_STC0m*
73 clkrat2stc[(CPU_SYS_HZ+CPU_REF_HZ/2)/CPU_REF_HZ]);
75 /* No clock disable, immediate change, busmaster high-speed */
76 *SYS_SCKCR=(0*SCKCR_PSTOPm)|(1*SCKCR_STCSm)|(0&SCKCR_SCKxm);
79 /* set 6x8 pixel font */
81 #else /* USE_FONT_6x8 */
82 /* set 8x8 pixel font */
84 #endif /* USE_FONT_6x8 */
85 //SHADDOW_REG_SET(DIO_P7DDR,0x10);
87 /* Setup chipselect outputs CS4 CS5 CS6 */
89 //SHADDOW_REG_SET(DIO_P7DDR,1|2|4);
91 /* Setup chipselect outputs CS3 CS2 CS1 CS0 */
92 //*DIO_PGDR |=2|4|8|0x10;
93 //SHADDOW_REG_SET(DIO_PGDDR,2|4|8|0x10);
95 /* setup chipselect 1 - XRAM */
96 *BUS_ABWCR&=~ABWCR_ABW1m; /* 16 bit width */
97 *BUS_ASTCR&=~ASTCR_AST1m; /* 2 states access */
98 *BUS_WCRL&=~(WCRL_W11m|WCRL_W10m);/* 0 additional wait states */
100 /* setup chipselect 2 - SGM_LCD */
101 *BUS_ABWCR|=ABWCR_ABW2m; /* 8 bit width */
102 *BUS_ASTCR|=ASTCR_AST2m; /* 3 states access */
103 *BUS_WCRL&=~(WCRL_W21m|WCRL_W20m);/* 0 additional wait states */
104 *BUS_WCRL|=1*WCRL_W21m; /* 0/1 additional wait state */
106 /* setup chipselect 3 - SRAM */
107 *BUS_ABWCR|=ABWCR_ABW3m; /* 8 bit width */
108 *BUS_ASTCR|=ASTCR_AST3m; /* 3 states access */
109 *BUS_WCRL&=~(WCRL_W31m|WCRL_W30m);/* 0 additional wait states */
111 /* setup chipselect 4 - IDE */
112 *BUS_ABWCR&=~ABWCR_ABW4m; /* 16 bit width */
113 *BUS_ASTCR|=ASTCR_AST4m; /* 3 states access */
114 *BUS_WCRH&=~(WCRH_W41m|WCRH_W40m);/* 0 additional wait states */
116 /* setup chipselect 5 - IDE */
117 *BUS_ABWCR&=~ABWCR_ABW5m; /* 16 bit width */
118 *BUS_ASTCR|=ASTCR_AST5m; /* 3 states access */
119 *BUS_WCRH&=~(WCRH_W51m|WCRH_W50m);/* 0 additional wait states */
121 /* setup chipselect 6 - KL41 */
122 *BUS_ABWCR|=ABWCR_ABW6m; /* 8 bit width */
123 *BUS_ASTCR|=ASTCR_AST6m; /* 3 states access */
124 *BUS_WCRH=WCRH_W61m|WCRH_W60m; /* 3 additional wait states */
126 /* crross cs wait| rd/wr wait | no burst and DRAM */
127 *BUS_BCRH=0*BCRH_ICIS1m | 0*BCRH_ICIS0m;
128 /* release | no DMAC buffer | no external wait */
129 /* **************************************************** */ //*BUS_BCRL=0*BCRL_BRLEm | 0*BCRL_WDBEm | 0*BCRL_WAITEm;
130 *DIO_PCDDR=0xff; /* A0-A7 are outputs */
131 *DIO_PBDDR=0xff; /* A8-A15 are outputs */
132 /* Setup full 20 address lines */
134 *DIO_PADDR=0x0f; /* A16-A19 are outputs */
135 /* number of address output signals */
136 *SYS_PFCR=__val2mfld(PFCR_AExm,20-8);
138 /* Stop all modules */
143 /*set power on for SCI4 module*/
144 *SYS_MSTPCRC&=~MSTPCRC_SCI4m;
146 /* show something on debug leds */
148 SHADDOW_REG_SET(DIO_P1DDR,0x0f);
151 /* Off TxD2 on Port PA.1 */
152 /* Off RxD2 on Port PA.2 */
158 /* Stop SCI4 communication */
159 // SCI4 is not aviable
163 /* Output TxD4 on Port P3.7, TxD0 on P3.0 */
164 /* RTS4 on Port P3.2 */
165 /* Input RxD4 on Port P3.6, RxD0 on P3.1 */
166 /* CTS4 on Port P3.3 */
168 SHADDOW_REG_SET(DIO_P3DDR,0x85);
170 /* Enables access to flash control registers */
171 *IIC_SCRX |= SCRX_FLSHEm;
173 if(((*FLM_FLMCR1) & FLMCR1_FWEm)!=0){
177 if (*((unsigned long *)0x4000)!=0xffffffff){
178 call_address(0x4000);
181 if (*((unsigned long *)0x200000)==0xff0055aa){
182 call_address(0x200004);