ARM: tegra: clock:Fix Sleeping while atomic in LP0
After enabling CONFIG_DEBUG_ATOMIC_SLEEP,during LP0 we see warning
regarding sleep in atomic region for clk_enable and clk_disable.
To fix this, we need to use clk_enable_locked and clk_disable_locked
instead.These functions do not acquire locks.
Change-Id: Ia654783de0cf72abac6847ac9630236f9f0d6ebb Signed-off-by: Peng Du <pdu@nvidia.com>
Reviewed-on: http://git-master/r/441348
(cherry picked from commit 518317f3e09c794e14de49f1afe47a93f92787ab)
Reviewed-on: http://git-master/r/448179 Reviewed-by: Matthew Pedro <mapedro@nvidia.com> Tested-by: Matthew Pedro <mapedro@nvidia.com>
gpu: nvgpu: return error from mutex_acquire() if pmu not initialized
In pmu_mutex_acquire(), we return zero (success) if
pmu->initialized is not set
Since mutex_acquire() was successful, we then call
pmu_mutex_release()
If now pmu->initialized is set in some other thread
then we proceed to validate the mutex owner and
end up causing below warning :
pmu_mutex_release: requester 0x00000000 NOT match owner 0x00000008
Hence to fix this return error from mutex_acquire()
and mutex_release() if pmu->initialized is not yet set
and in that case we proceed to call elpg enable/disable
Change-Id: Ib132b9feeb85a7b7bacfa7aeceb646aa89d54ece Signed-off-by: Zheng Liu <zhliu@nvidia.com>
Reviewed-on: http://git-master/r/440520
GVS: Gerrit_Virtual_Submit Tested-by: Mike Thompson <mikthompson@nvidia.com> Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Change-Id: If0f769bceaf6edcd8fe5d2fbd067a2ed3a81cca2 Signed-off-by: Zheng Liu <zhliu@nvidia.com>
Reviewed-on: http://git-master/r/440519
GVS: Gerrit_Virtual_Submit Tested-by: Mike Thompson <mikthompson@nvidia.com> Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Change-Id: I842150ecccb722a93b7b80b3c87dcf1ceb13e7b5 Signed-off-by: Zheng Liu <zhliu@nvidia.com>
Reviewed-on: http://git-master/r/440518 Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit Tested-by: Mike Thompson <mikthompson@nvidia.com> Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Change-Id: I8c1acb14d62df51cac535b2b78df0070744a5b66 Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/436700
(cherry picked from commit 6eff7bd5a3a858e92c1088c102b21e86e12bf35b)
Reviewed-on: http://git-master/r/439915 Tested-by: Jong Kim <jongk@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Change-Id: If5db728a0bca436f0c12ec3de56c4fec9b3d3328 Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/436316
(cherry picked from commit bec916df2e450d763a912be37b783450aaf5b862)
Reviewed-on: http://git-master/r/439914 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Jong Kim <jongk@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Jon Mayo [Wed, 18 Jun 2014 23:01:10 +0000 (16:01 -0700)]
video: tegra: dc: move cursor into core driver
Move cursor routines into the core driver, provide a small abstraction
layer to update the cursor.
Change-Id: Idfa1c6b313806de6a5d34f9f05592574f5829933 Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/436315
(cherry picked from commit 14e65ae70661462aa50f424a04a65a7c0efd9ff9)
Reviewed-on: http://git-master/r/439913 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Jong Kim <jongk@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Roger Hsieh [Mon, 7 Jul 2014 07:42:39 +0000 (15:42 +0800)]
ARM: ardbeg: enable throttle only with compatible machines
Mostly we enabled different machines in defconfig. The calls in
the board file should ensure it's executing with the compatible
machines, or race condition will be happened.
usb: gadget: tegra: handle the case when host reboots
Some hosts during booting first supply vbus and then
send setup packets after x seconds. In this case we detect
as non-standard. Handle this case by setting to SDP.
Also adding condition to avoid unnecessary icon
notifications.
Philip Rakity [Wed, 4 Jun 2014 11:37:30 +0000 (12:37 +0100)]
usb: phy: tegra: QC2 speed up charger recogniion
The QC2 Wall Charger needs to be reset only when
we boot or reboot the system. This is because
the wall charger will have already defaulted to a DCP.
Since the internal logic in the Wall Charger will not
see D+/D- programmed during the time available.
If we just plug in the charger then it will be recognised
in time so no reset is necessary. Removes 1.5s of delay.
Arto Merilainen [Mon, 7 Jul 2014 12:50:21 +0000 (15:50 +0300)]
devfreq: Account only powered time in trans_stat
This patch modifies devfreq to account only the time a device is
powered in trans_stat. In addition, this patch also fixes a race
in trans_stat maintenance in cases where the node is readed at
the same time the transition table is being updated by frequency
re-estimation.
Change-Id: I6e4341317b6dda88d69028c9f67785400e5a7a65 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/435174 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Prajakta Gudadhe <pgudadhe@nvidia.com> Reviewed-by: Samuel Russell <samuelr@nvidia.com> Tested-by: Samuel Russell <samuelr@nvidia.com> Reviewed-by: Ilan Aelion <iaelion@nvidia.com>
Timo Alho [Mon, 7 Jul 2014 05:44:56 +0000 (08:44 +0300)]
tegra: dtb: sysedp: enable sysedp only on P1761 with battery
Previously, sysedp was attempted to enabled on non-battery versions of
P1761. This caused sysedp_batmon_calc to fail with -EFAULT during
probing as battery power supply was not available.
arm64: guarantee correct tlb flushes with preeption on
We need to guarantee that our thread hasn't switched
cores between being asked to flush the local core's
tlb and having actually performed the task. If it
has, we need to perform a global tlbi.
Change-Id: I4b1bc5fbe53a7d35a2442753d8fe3f0ae86415ac Signed-off-by: Rich Wiley <rwiley@nvidia.com>
Reviewed-on: http://git-master/r/433805
GVS: Gerrit_Virtual_Submit Reviewed-by: Peng Du <pdu@nvidia.com> Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-by: Mitch Luban <mluban@nvidia.com>
Channel and gpfifo allocations are entirely separated from each
other, however, the code here assumes that active channel means
that the channel also has a gpfifo.
This reverts commit a24602f094380539788696d1b1567a4f4d914b17 which
added gpfifo dump. Changing debug dumping to be safe requires
refactoring the channel release code to use proper locking.
Increase the wait delays in do_idle() to 2000 mS and make use
of msleep instead of mdelays
Also, to check if GPU is rail gated or not, add a do-while()
loop which will keep checking the status and bail out as soon
as GPU is rail gated
This increase in delays is required to allow GPU sufficient
time to complete its work and get rail gated
These delays are specially needed during stress testing where
it is possible that a large amount of GPU work is blocked
during do_idle() and then it might take more time to complete
it while next do_idle() is waiting for it
Also, remove waiting on API gk20a_wait_channel_idle() for each
channels since it is sufficient to wait for refcount to be 1
gk20a_busy() call in channel_syncpt_incr() and corresponding
gk20a_idle() call in channel_update() are redundant since they
are already encapsulated inside another pair of busy/idle calls
This busy/idle pair will be called only from submit_gpfifo()
and submit_gpfifo() already has its own busy/idle which it
preserves for whole path and hence this redundant pair can be
removed
Also, this prevents a dead lock scenario while do_idle() is in
progress as follows :
- in submit_gpfifo() we call first gk20a_busy() which acquires
busy read semaphore
- in do_idle() we acquire busy write semaphore and wait for
current jobs to finish
- now submit_gpfifo() encounters second gk20a_busy() and requests
busy read semaphore again
- this results in dead lock where do_idle() is waiting for
submit_gpfifo() to complete and submit_gpfifo() is waiting for
busy lock held by do_idle() and hence it cannot complete
gpu: nvgpu: fix race between do_idle() and unrailgate()
While we are executing do_idle() API, it is possible that
unrailgate() gets invoked in midst of idling the GPU and
this can result in failure of do_idle()
To prevent simultaneous execution of these methods,
add a mutex railgate_lock and acquire it during
do_idle() and unrailgate() APIs
Also, keep this lock held if do_idle() is successful.
In success, lock will be released in do_unidle(),
otherwise release this lock before returning
Note that this lock should not be held in railgate() API
since we do not want it to be blocked during do_idle()
Allen Yu [Wed, 2 Jul 2014 07:14:24 +0000 (15:14 +0800)]
media: tegra: nvavp: fix deadlock issue
In nvavp_pushbuffer_update(), we acquire channel_info->pushbuffer_lock first
then nvavp->open_lock. While in clock_disable_handler(), open_lock is acquired
before pushbuffer_lock, causing the deadlock if clock_disable_work happens to
be executing while running nvavp_pushbuffer_update().
This change reorder the locks in clock_disable_handler to avoid deadlock issue.
And also in tegra_nvavp_release(), need to release nvavp->open_lock first before
calling nvavp_uninit(), since nvavp_uninit() need to cancel clock_disable_work
in a synchronous manner.
Peng Du [Mon, 30 Jun 2014 18:03:19 +0000 (11:03 -0700)]
arm64: tegra: misc fixes to hardwood driver
* Set NS bit when kernel is non-secure
* fix potential race in late_init
* enable hotplug notifier in late_init
* set buf occupied if immediately available
* better debugging print
Change-Id: I7acd736888f05facc559c7c965e20aea6f43060c Signed-off-by: Peng Du <pdu@nvidia.com>
Reviewed-on: http://git-master/r/432822 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Jinyoung Park [Tue, 1 Jul 2014 07:51:24 +0000 (16:51 +0900)]
mmc: sdhci: tegra: Add setting for dma-mask
Currently, there is no binding for coherent_dma_mask and dma_mask
in device tree. If sdhci-tegra driver is probed from DT,
coherent_dma_mask will be set to 32 bit as DT default and
dma_mask will be NULL.
So added coherent_dma_mask setting for each Tegra SKUs.
And if dma_mask is NULL, set it to coherent_dma_mask.
Possible null pointer derefernce occurs when
nvmap_pages return NULL. Add null pointer check after
nvmap_pages call to prevent null pointer dereference in
sg_alloc_table_from_pages
Manikanta [Mon, 30 Jun 2014 08:22:28 +0000 (13:52 +0530)]
net: wireless: bcmdhd: Fix LP0 in case of wifi tethering
PROPTX_STATUS periodically sends useful information (such as
flow control info, RSSI etc) to the host, this prevents host from
going into LP0 mode. Disable dhd_pm_callback pm notifier
to fix this issue.
ASoC: Tegra: Refactor offload to handle multiple BE
- Added virtual mixer and switch to support multiple BE
- One FE can be connected to multiple BE, mixer control can be used
to select the path
- Fix crash if no path is selected
Terje Bergstrom [Fri, 27 Jun 2014 10:45:02 +0000 (13:45 +0300)]
gpu: nvgpu: Wait for idle via FIFO registers
Wait for engine idle via FIFO's engine status instead of submitting
WFI to channel. Submitting WFI and waiting is not robust, and wait
might invoke debug dump which cannot be done while powering down.
Vijayakumar [Fri, 27 Jun 2014 09:20:31 +0000 (14:50 +0530)]
gpu:nvgpu:fix powergate disabling order
ELPG has to disabled before we write to clock gating registers
If ELPG is engaged during clock gating register write it will
cause error in ELPG engine
drivers: clocksource: add CPU PM notifier for ARM architected timer
Few control settings done in architected timer as part of initialisation
can be lost when CPU enters deeper power states. They need to be
restored when the CPU is (warm)reset again.
This patch adds CPU PM notifiers to save the counter control register
when entering low power modes and restore it when CPU exits low power.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
Change-Id: I0bad683961e4b72835ad40edf2c9ac9e0f78fad0
Reviewed-on: http://git-master/r/350844 Reviewed-by: Bo Yan <byan@nvidia.com> Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/427526 Tested-by: Andrey Trachenko <atrachenko@nvidia.com>
GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Krishna Reddy [Sat, 28 Jun 2014 03:13:05 +0000 (20:13 -0700)]
arm: tegra: remove memory for ramoops in correct order
memory for ramoops need to be removed before cma dev's setup.
more over, the memory need to be removed from mem block instead
of reserve.
Bug 200016405
Jon Mayo [Fri, 16 May 2014 00:45:08 +0000 (17:45 -0700)]
video: tegra: dc: skip duplicate CMU update
Skip updating CMU on first boot, and restore CMU after disable or
suspend. Use dc->pdata->cmu_enable to select initial state of cmu, and
move the current cmu status out of dc->pdata and into dc->cmu_enabled.
Remove unused flag TEGRA_DC_FLAG_CMU_ENABLE.
Terje Bergstrom [Thu, 26 Jun 2014 10:26:19 +0000 (13:26 +0300)]
gpu: nvgpu: Clear channel class on open
Channel class needs to be cleared when a channel is opened. Otherwise
previously used channel remains, and we can accidentally use KEPLER_C
methods even if KEPLER_C is not allocated.
Deepak Nibade [Wed, 25 Jun 2014 13:27:23 +0000 (18:57 +0530)]
gpu: nvgpu: fix possible PMU isr race
Possible race description :
- while PMU is booting, it sends messages to kernel which we process
in gk20a_pmu_isr()
- but when messages are processed it is possible that we are on the way
to rail gate the GPU and we have already called pmu_destroy()
- this could lead to hangs if while processing messages, GR is
already off
To fix this, introduce another mutex isr_enable_lock and a flag to
turn on/off ISRs
- when we enable PMU, get the lock and set the flag
- in pmu_destroy(), get the lock and remove the flag
- in pmu_isr(), take the lock, check if flag is set or not. If flag
is not set return, otherwise proceed with the messages
In case integration time for the sensor is not properly set,
User space may query the updated value of a sensor before an event
is generated from the sensor. Kernel driver should not send a stale or
invalid event in such cases, else it may impact performance and in some
cases, the user space application may behave in some undesirable way.
This change checks for such invalid events and makes sure such values
are not sent to user space.
Jajambo Liao [Mon, 23 Jun 2014 10:29:44 +0000 (18:29 +0800)]
input: misc: change module init priority.
change compass & pressure module init priority as
late_initcall.
That can make sure compass & pressure will be loaded
after mpu driver.
- modify CONFIG_INV_MPU, CONFIG_INV_AKM8975, CONFIG_INV_BMP180
to be "=y", build those module as static library
- remove "insmod inv-mpu.ko", "insmod inv-ak8975.ko"
"insmod inv-bmp180.ko" command from init script
- set init priority of akm89xx/bmp180 as late_initcall
That will make sure system always loaded akm89xx/bmp180 after
inv-mpu module when those modules was builded as static library.
Jajambo Liao [Wed, 18 Jun 2014 05:44:02 +0000 (13:44 +0800)]
arm: tegra: config: build invensens as .so
change invensens build method from dynamic library to
static library
- modify CONFIG_INV_MPU, CONFIG_INV_AKM8975, CONFIG_INV_BMP180
to be "=y", build those module as static library
- remove "insmod inv-mpu.ko", "insmod inv-ak8975.ko"
"insmod inv-bmp180.ko" command from init script
- set init priority of akm89xx/bmp180 as late_initcall
That will make sure system always loaded akm89xx/bmp180 after
inv-mpu module when those modules was builded as static library.
Deepak Nibade [Tue, 24 Jun 2014 12:41:25 +0000 (18:11 +0530)]
gpu: nvgpu: do not abort probe if secure page alloc fails
Do not abort GPU probe if secure page alloc fails.
We can just note that this allocation failed (using bool
secure_alloc_ready) and prevent further secure memory
allocation if this flag is not set.
Alex Frid [Wed, 18 Jun 2014 22:02:24 +0000 (15:02 -0700)]
ARM: tegra13: dvfs: Add GPU SiMon offsets
Added GPU Vmin -20mV offset for high SiMon grade on Tegra13 platforms.
Constructed the respective GPU DVFS table with offsets applied, and
SiMon notifier to switch between tables w/wo offset. Since no SiMon
grading is available only original DVFS table with no offset is used
for now.
Change-Id: I959ed2142e478b9693a5bc425ef2165b43210bab Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/425035 Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com> Tested-by: Sai Gurrappadi <sgurrappadi@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Alex Frid [Wed, 18 Jun 2014 03:53:40 +0000 (20:53 -0700)]
ARM: tegra13: dvfs: Specify DFLL tuning SiMon mask
Specified DFLL tuning mask to toggle settings based on SiMon grade.
Changed defaults used before SiMon grade is determined after boot to
slower settings.
Change-Id: Ibcf25c418fe0fa10af0778599a701f11a9f90719 Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/424908 Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com> Tested-by: Sai Gurrappadi <sgurrappadi@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Change-Id: Ia7fa83db6a6ee003c0e1211c8a7fb9ac89630487 Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/424907 Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com> Tested-by: Sai Gurrappadi <sgurrappadi@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Alex Frid [Wed, 18 Jun 2014 02:57:15 +0000 (19:57 -0700)]
ARM: tegra: dvfs: Add SiMon grading to DFLL tuning
Added dependency of DFLL tuning settings on SiMon grading as follows:
- Selected set of tuning bits specified by platform specific SiMon
mask is toggled when SiMon grade is changing from zero to non-zero
(high) grade, or vice versa.
- The same toggle mask is applied to settings in low and high voltage
tuning ranges.
- SiMon mask can be applied only while DFLL is tuned for low voltage
range
Change-Id: I10cb69ea30c7773042c640d41e0dc0c99038ab7d Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/424906 Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com> Tested-by: Sai Gurrappadi <sgurrappadi@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Change-Id: Ib8c51f75a5a1582aa8c0117ee05ed044de5894a9 Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/424905 Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com> Tested-by: Sai Gurrappadi <sgurrappadi@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Usage of SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_ANY_ID) is
causing device hang when BRCM chipsets BCM433341 are used.
This is because SDIO_DEVICE MACRO uses, SDIO_ANY_ID for class.
Use SDIO_CLASS_NONE instead resolves device hang issue.
Alex Frid [Sat, 21 Jun 2014 07:52:37 +0000 (00:52 -0700)]
ARM: tegra dvfs: Keep DVFS rate for disabled GPU clock
Preserved DVFS rate for single clock GPU rail when clock is disabled
(instead of setting zero rate). In this case GPU rail is turned off
explicitly, anyway. However with non-zero DVFS rate voltage level at
regulator is appropriately updated when temperature is changes while
rail is off.
Seema Khowala [Fri, 20 Jun 2014 18:36:30 +0000 (11:36 -0700)]
arm: tegra: pinmux : enable e_input of sdmmc clk
For all SDMMC controllers, E_INPUT of CLK pad should be
enabled since loopback CLK (Zi of CLK pad) is used to
latch RESP/DATA coming from external device.
If not enabled, you will see RESP/DATA time outs.
Change-Id: I85f7d9a89362529b6909fe56376e9ac9d8b4dfd2 Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/345674 Signed-off-by: Peng Du <pdu@nvidia.com>
Reviewed-on: http://git-master/r/426713 Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Tested-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
projects / sojka / nv-tegra / linux-3.10.git / log