platform: tegra: Define DDR Tap/trim varibles

Bug 1563244

Change-Id: Ic4a43df8d11f87b3f62c652109abf540874224c4
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>

diff --git a/include/linux/platform_data/mmc-sdhci-tegra.h b/include/linux/platform_data/mmc-sdhci-tegra.h
index 57ccd62194cde74736e2dd7984e6a580e075500f..0573ed374935468981756b1d7b54fa864a478e58 100644 (file)
--- a/include/linux/platform_data/mmc-sdhci-tegra.h
+++ b/include/linux/platform_data/mmc-sdhci-tegra.h
@@ -55,7 +55,10 @@ struct tegra_sdhci_platform_data {
        unsigned int max_clk_limit;
        unsigned int ddr_clk_limit;
        unsigned int tap_delay;
+       bool is_ddr_tap_delay;
+       unsigned int ddr_tap_delay;
        unsigned int trim_delay;
+       bool is_ddr_trim_delay;
        unsigned int ddr_trim_delay;
        unsigned int dqs_trim_delay;
        unsigned int uhs_mask;