ARM: tegra: ceres: change csi/cilcd clock

Remove cilcd clock in T148.
Change max clock for csi to 102MHz from 100MHz.

Bug 1180011

Change-Id: Id12ec0039477c6cf1f4cedd34b54382e1578a39b
Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-on: http://git-master/r/198572
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

diff --git a/arch/arm/mach-tegra/tegra14_dvfs.c b/arch/arm/mach-tegra/tegra14_dvfs.c
index 993d568d7cc41bdcd8afd260497a5782c703f35e..2bf5f3711d488a64d8ef221c043e73c4afdd6297 100644 (file)
--- a/arch/arm/mach-tegra/tegra14_dvfs.c
+++ b/arch/arm/mach-tegra/tegra14_dvfs.c
@@ -198,7 +198,7 @@ static struct dvfs core_dvfs_table[] = {
 #endif
        /* Core voltages (mV):              810,    850,    900,    950,   1000,   1050,   1100 */
        /* Clock limits for I/O peripherals */
-       CORE_DVFS("csi",  -1, 1, KHZ,        1,      1, 75000, 75000, 75000, 84400, 100000),
+       CORE_DVFS("csi",  -1, 1, KHZ,        1,      1, 75000, 75000, 75000, 84400, 102000),
        CORE_DVFS("cilab",  -1, 1, KHZ,        1,      1, 102000, 102000, 102000, 114700, 136000),
        CORE_DVFS("cilcd",  -1, 1, KHZ,        1,      1, 102000, 102000, 102000, 114700, 136000),
        CORE_DVFS("cile",  -1, 1, KHZ,        1,      1, 102000, 102000, 102000, 114700, 136000),