Currently, if CONFIG_TEGRA_LP1_LOW_COREVOLTAGE is enabled,
we decrease core voltage to a level specified via lp1_core_volt_low
in each platform's board file.
Add another level, lp1_core_volt_low_cold, which will be used if
there's a low temperature core voltage floor set during LP1 entry.
Only one voltage floor exists for T30 and T114, so only one additional
low voltage entry has been added.
Bug
1261915
Change-Id: I614a4176b0bf68d6607a104a980d38589ebd3046
Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-on: http://git-master/r/216364
(cherry picked from commit
b12e9b71552b89664dd8bdfc26e5e33cc9b45056)
Reviewed-on: http://git-master/r/226437
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
.i2c_base_addr = 0,
.pmuslave_addr = 0,
.core_reg_addr = 0,
+ .lp1_core_volt_low_cold = 0,
.lp1_core_volt_low = 0,
.lp1_core_volt_high = 0,
#endif
.i2c_base_addr = 0,
.pmuslave_addr = 0,
.core_reg_addr = 0,
+ .lp1_core_volt_low_cold = 0,
.lp1_core_volt_low = 0,
.lp1_core_volt_high = 0,
#endif
.i2c_base_addr = TEGRA_I2C5_BASE,
.pmuslave_addr = 0xB0,
.core_reg_addr = 0x2B,
- .lp1_core_volt_low = 0x33,
+ .lp1_core_volt_low_cold = 0x33,
+ .lp1_core_volt_low = 0x2e,
.lp1_core_volt_high = 0x42,
#endif
};
.i2c_base_addr = 0,
.pmuslave_addr = 0,
.core_reg_addr = 0,
+ .lp1_core_volt_low_cold = 0,
.lp1_core_volt_low = 0,
.lp1_core_volt_high = 0,
#endif
unsigned int i2c_base_addr;
unsigned int pmuslave_addr;
unsigned int core_reg_addr;
+ unsigned int lp1_core_volt_low_cold;
unsigned int lp1_core_volt_low;
unsigned int lp1_core_volt_high;
#endif