xhci: tegra: set HS_DISCON_LEVEL to 3'b111

Set HS_DISCON_LEVEL in xusb padctl register
USB2_BIAS_PAD_CTL_0 from 3'b101 to 3'b111.

Bug 1454282

Change-Id: I48916435e9a142a0674195d8b690c7f8ff376525
Signed-off-by: Joy Wang <joyw@nvidia.com>
Reviewed-on: http://git-master/r/364302
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: Henry Lin <henryl@nvidia.com>

diff --git a/drivers/usb/host/xhci-tegra.c b/drivers/usb/host/xhci-tegra.c
index cfa787d4abe9ceac23831e4b423b84d641f31794..707309c1894b0f2709cec45e41160ca4dbc3660d 100644 (file)
--- a/drivers/usb/host/xhci-tegra.c
+++ b/drivers/usb/host/xhci-tegra.c
@@ -4139,7 +4139,7 @@ static const struct tegra_xusb_soc_config tegra114_soc_config = {
        .hs_slew = (0xE << 6),
        .ls_rslew_pad0 = (0x3 << 14),
        .ls_rslew_pad1 = (0x0 << 14),
-       .hs_disc_lvl = (0x5 << 2),
+       .hs_disc_lvl = (0x7 << 2),
        .spare_in = 0x0,
        .supply = {
                .utmi_vbuses = {"usb_vbus0", "usb_vbus1", "usb_vbus2",},
@@ -4162,7 +4162,7 @@ static const struct tegra_xusb_soc_config tegra124_soc_config = {
        .ls_rslew_pad0 = (0x3 << 14),
        .ls_rslew_pad1 = (0x0 << 14),
        .ls_rslew_pad2 = (0x0 << 14),
-       .hs_disc_lvl = (0x5 << 2),
+       .hs_disc_lvl = (0x7 << 2),
        .spare_in = 0x1,
        .supply = {
                .utmi_vbuses = {"usb_vbus0", "usb_vbus1", "usb_vbus2",},