arm: tegra13: soctherm: use PLL-TSOSC to throttle

For certain older revs of ATE, we will use use PLL-TSOSC (instead of
the CPU-TSOSCs) on T132 devices to drive throttling (HW and SW) and
shutdown to avoid random shutdown issues seen on some platforms.

Switch to PLL-TSOSC instead of CPU-TSOSC in all t132ref platforms.

Bug 1468124

Change-Id: I432676d12c2ad35910f70e9dc8225db5480e6f53
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/396157

diff --git a/arch/arm/mach-tegra/board-ardbeg-power.c b/arch/arm/mach-tegra/board-ardbeg-power.c
index 12fbd05c779b660cb2f8c093a200e11f73b7d3f7..bcb2b571c3f1a71bf00692da0070f22d985e0acd 100644 (file)
--- a/arch/arm/mach-tegra/board-ardbeg-power.c
+++ b/arch/arm/mach-tegra/board-ardbeg-power.c
@@ -609,6 +609,46 @@ static struct soctherm_platform_data ardbeg_soctherm_data = {
        },
 };
 
+/* Only the diffs from ardbeg_soctherm_data structure */
+static struct soctherm_platform_data t132ref_v1_soctherm_data = {
+       .therm = {
+               [THERM_CPU] = {
+                       .zone_enable = true,
+                       .passive_delay = 1000,
+                       .hotspot_offset = 6000,
+               },
+               [THERM_PLL] = {
+                       .zone_enable = true,
+                       .passive_delay = 1000,
+                       .num_trips = 3,
+                       .trips = {
+                               {
+                                       .cdev_type = "tegra-shutdown",
+                                       .trip_temp = 99000,
+                                       .trip_type = THERMAL_TRIP_CRITICAL,
+                                       .upper = THERMAL_NO_LIMIT,
+                                       .lower = THERMAL_NO_LIMIT,
+                               },
+                               {
+                                       .cdev_type = "tegra-heavy",
+                                       .trip_temp = 96000,
+                                       .trip_type = THERMAL_TRIP_HOT,
+                                       .upper = THERMAL_NO_LIMIT,
+                                       .lower = THERMAL_NO_LIMIT,
+                               },
+                               {
+                                       .cdev_type = "cpu-balanced",
+                                       .trip_temp = 86000,
+                                       .trip_type = THERMAL_TRIP_PASSIVE,
+                                       .upper = THERMAL_NO_LIMIT,
+                                       .lower = THERMAL_NO_LIMIT,
+                               },
+                       },
+                       .tzp = &soctherm_tzp,
+               },
+       },
+};
+
 static struct soctherm_throttle battery_oc_throttle = {
        .throt_mode = BRIEF,
        .polarity = SOCTHERM_ACTIVE_LOW,
@@ -673,6 +713,7 @@ int __init ardbeg_soctherm_init(void)
        u32 base_ft, shft_ft;
        struct board_info pmu_board_info;
        struct board_info board_info;
+       enum soctherm_therm_id therm_cpu;
 
        tegra_get_board_info(&board_info);
 
@@ -682,26 +723,41 @@ int __init ardbeg_soctherm_init(void)
                                ardbeg_therm_pop, sizeof(ardbeg_therm_pop));
        }
 
+       /* Bowmore and P1761 are T132 platforms: ATE rev check (TODO) */
+       if (board_info.board_id == BOARD_E1971 ||
+                       board_info.board_id == BOARD_P1761 ||
+                       board_info.board_id == BOARD_E1991) {
+               memcpy(&ardbeg_soctherm_data.therm[THERM_CPU],
+                       &t132ref_v1_soctherm_data.therm[THERM_CPU],
+                       sizeof(t132ref_v1_soctherm_data.therm[THERM_CPU]));
+               memcpy(&ardbeg_soctherm_data.therm[THERM_PLL],
+                       &t132ref_v1_soctherm_data.therm[THERM_PLL],
+                       sizeof(t132ref_v1_soctherm_data.therm[THERM_PLL]));
+               therm_cpu = THERM_PLL; /* override CPU zone with PLL zone */
+       } else {
+               therm_cpu = THERM_CPU;
+       }
+
        /* do this only for supported CP,FT fuses */
        if ((tegra_fuse_calib_base_get_cp(&base_cp, &shft_cp) >= 0) &&
            (tegra_fuse_calib_base_get_ft(&base_ft, &shft_ft) >= 0)) {
                tegra_platform_edp_init(
-                       ardbeg_soctherm_data.therm[THERM_CPU].trips,
-                       &ardbeg_soctherm_data.therm[THERM_CPU].num_trips,
+                       ardbeg_soctherm_data.therm[therm_cpu].trips,
+                       &ardbeg_soctherm_data.therm[therm_cpu].num_trips,
                        7000); /* edp temperature margin */
                tegra_platform_gpu_edp_init(
                        ardbeg_soctherm_data.therm[THERM_GPU].trips,
                        &ardbeg_soctherm_data.therm[THERM_GPU].num_trips,
                        7000);
                tegra_add_cpu_vmax_trips(
-                       ardbeg_soctherm_data.therm[THERM_CPU].trips,
-                       &ardbeg_soctherm_data.therm[THERM_CPU].num_trips);
+                       ardbeg_soctherm_data.therm[therm_cpu].trips,
+                       &ardbeg_soctherm_data.therm[therm_cpu].num_trips);
                tegra_add_tgpu_trips(
                        ardbeg_soctherm_data.therm[THERM_GPU].trips,
                        &ardbeg_soctherm_data.therm[THERM_GPU].num_trips);
                tegra_add_vc_trips(
-                       ardbeg_soctherm_data.therm[THERM_CPU].trips,
-                       &ardbeg_soctherm_data.therm[THERM_CPU].num_trips);
+                       ardbeg_soctherm_data.therm[therm_cpu].trips,
+                       &ardbeg_soctherm_data.therm[therm_cpu].num_trips);
                tegra_add_core_vmax_trips(
                        ardbeg_soctherm_data.therm[THERM_PLL].trips,
                        &ardbeg_soctherm_data.therm[THERM_PLL].num_trips);
@@ -713,8 +769,8 @@ int __init ardbeg_soctherm_init(void)
                board_info.board_id == BOARD_E1991 ||
                board_info.board_id == BOARD_E1922) {
                tegra_add_cpu_vmin_trips(
-                       ardbeg_soctherm_data.therm[THERM_CPU].trips,
-                       &ardbeg_soctherm_data.therm[THERM_CPU].num_trips);
+                       ardbeg_soctherm_data.therm[therm_cpu].trips,
+                       &ardbeg_soctherm_data.therm[therm_cpu].num_trips);
                tegra_add_gpu_vmin_trips(
                        ardbeg_soctherm_data.therm[THERM_GPU].trips,
                        &ardbeg_soctherm_data.therm[THERM_GPU].num_trips);

diff --git a/arch/arm/mach-tegra/board-norrin-power.c b/arch/arm/mach-tegra/board-norrin-power.c
index 1e0e48b6076844edb12a55bf2fd0a3b00ac45555..8b1fad7fcbe76e9cf4469a3004b42f8c2d8bb010 100644 (file)
--- a/arch/arm/mach-tegra/board-norrin-power.c
+++ b/arch/arm/mach-tegra/board-norrin-power.c
@@ -216,30 +216,6 @@ static struct soctherm_platform_data norrin_soctherm_data = {
                        .zone_enable = true,
                        .passive_delay = 1000,
                        .hotspot_offset = 6000,
-                       .num_trips = 3,
-                       .trips = {
-                               {
-                                       .cdev_type = "tegra-shutdown",
-                                       .trip_temp = 101000,
-                                       .trip_type = THERMAL_TRIP_CRITICAL,
-                                       .upper = THERMAL_NO_LIMIT,
-                                       .lower = THERMAL_NO_LIMIT,
-                               },
-                               {
-                                       .cdev_type = "tegra-heavy",
-                                       .trip_temp = 99000,
-                                       .trip_type = THERMAL_TRIP_HOT,
-                                       .upper = THERMAL_NO_LIMIT,
-                                       .lower = THERMAL_NO_LIMIT,
-                               },
-                               {
-                                       .cdev_type = "cpu-balanced",
-                                       .trip_temp = 90000,
-                                       .trip_type = THERMAL_TRIP_PASSIVE,
-                                       .upper = THERMAL_NO_LIMIT,
-                                       .lower = THERMAL_NO_LIMIT,
-                               },
-                       },
                        .tzp = &soctherm_tzp,
                },
                [THERM_GPU] = {
@@ -288,6 +264,31 @@ static struct soctherm_platform_data norrin_soctherm_data = {
                },
                [THERM_PLL] = {
                        .zone_enable = true,
+                       .passive_delay = 1000,
+                       .num_trips = 3,
+                       .trips = {
+                               {
+                                       .cdev_type = "tegra-shutdown",
+                                       .trip_temp = 99000,
+                                       .trip_type = THERMAL_TRIP_CRITICAL,
+                                       .upper = THERMAL_NO_LIMIT,
+                                       .lower = THERMAL_NO_LIMIT,
+                               },
+                               {
+                                       .cdev_type = "tegra-heavy",
+                                       .trip_temp = 96000,
+                                       .trip_type = THERMAL_TRIP_HOT,
+                                       .upper = THERMAL_NO_LIMIT,
+                                       .lower = THERMAL_NO_LIMIT,
+                               },
+                               {
+                                       .cdev_type = "cpu-balanced",
+                                       .trip_temp = 86000,
+                                       .trip_type = THERMAL_TRIP_PASSIVE,
+                                       .upper = THERMAL_NO_LIMIT,
+                                       .lower = THERMAL_NO_LIMIT,
+                               },
+                       },
                        .tzp = &soctherm_tzp,
                },
        },
@@ -315,23 +316,27 @@ int __init norrin_soctherm_init(void)
        u32 base_ft, shft_ft;
        struct board_info pmu_board_info;
        struct board_info board_info;
+       enum soctherm_therm_id therm_cpu;
 
        tegra_get_board_info(&board_info);
 
+       /* For T132 platforms: ATE rev check (TODO) */
+       therm_cpu = THERM_PLL;
+
        /* do this only for supported CP,FT fuses */
        if ((tegra_fuse_calib_base_get_cp(&base_cp, &shft_cp) >= 0) &&
            (tegra_fuse_calib_base_get_ft(&base_ft, &shft_ft) >= 0)) {
                tegra_platform_edp_init(
-                       norrin_soctherm_data.therm[THERM_CPU].trips,
-                       &norrin_soctherm_data.therm[THERM_CPU].num_trips,
+                       norrin_soctherm_data.therm[therm_cpu].trips,
+                       &norrin_soctherm_data.therm[therm_cpu].num_trips,
                        7000); /* edp temperature margin */
                tegra_platform_gpu_edp_init(
                        norrin_soctherm_data.therm[THERM_GPU].trips,
                        &norrin_soctherm_data.therm[THERM_GPU].num_trips,
                        7000);
                tegra_add_cpu_vmax_trips(
-                       norrin_soctherm_data.therm[THERM_CPU].trips,
-                       &norrin_soctherm_data.therm[THERM_CPU].num_trips);
+                       norrin_soctherm_data.therm[therm_cpu].trips,
+                       &norrin_soctherm_data.therm[therm_cpu].num_trips);
                tegra_add_tgpu_trips(
                        norrin_soctherm_data.therm[THERM_GPU].trips,
                        &norrin_soctherm_data.therm[THERM_GPU].num_trips);
@@ -344,8 +349,8 @@ int __init norrin_soctherm_init(void)
                board_info.board_id == BOARD_E1971 ||
                board_info.board_id == BOARD_E1991) {
                tegra_add_cpu_vmin_trips(
-                       norrin_soctherm_data.therm[THERM_CPU].trips,
-                       &norrin_soctherm_data.therm[THERM_CPU].num_trips);
+                       norrin_soctherm_data.therm[therm_cpu].trips,
+                       &norrin_soctherm_data.therm[therm_cpu].num_trips);
                tegra_add_gpu_vmin_trips(
                        norrin_soctherm_data.therm[THERM_GPU].trips,
                        &norrin_soctherm_data.therm[THERM_GPU].num_trips);