pcie: host: tegra: fixes aspm l1 count

fixes aspm l1 enablement by checking only bit-1 instead
of checking bits-0 and 1 which is actually for both L0s
and L1

Change-Id: Id2a27f18d416488abc1fb9438098bc5938e6e791
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: http://git-master/r/772043
(cherry picked from commit 9adf2cfd50c0ff0c441c6e9b50c512f0ffa155c0)
Reviewed-on: http://git-master/r/777291
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index a60d892b58db75631d452a97b02b9b99c826a259..79cedd9889f6e6cdb4f988492549b2d23d65bfdf 100644 (file)
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -194,7 +194,7 @@
 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK   0x3fff0000
 #define RP_LINK_CONTROL_STATUS_NEG_LINK_WIDTH  (0x3F << 20)
 #define RP_LINK_CONTROL_STATUS_L0s_ENABLED             0x00000001
-#define RP_LINK_CONTROL_STATUS_L1_ENABLED              0x00000003
+#define RP_LINK_CONTROL_STATUS_L1_ENABLED              0x00000002
 
 #define NV_PCIE2_RP_RSR                                        0x000000A0
 #define NV_PCIE2_RP_RSR_PMESTAT                                (1 << 16)