ARM: tegra11: clock: set IDDQOVERIDE for UTMIPLL

Setting IDDQ_OVERRIDE for UTMIPLL by default,
otherwise power is consumed on UTMIPLL rail if no
usb device is active. Power is also seen
high once resume from LP0 if it is not set.

Bug 1174123
Bug 1215521

Reviewed-on: http://git-master/r/191177
(cherry picked from commit a0a0ceeeec6a6dbf329e9bd5dcb28b13a9a3b229)

Change-Id: Idb76aa8c5f3f8c722800ef5e1a2493fbc1160cf7
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/193068
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

diff --git a/arch/arm/mach-tegra/tegra11_clocks.c b/arch/arm/mach-tegra/tegra11_clocks.c
index 06a48f2d8aaace6d6d38d9ca520256089149e4e9..682112a526e6265fcb1e4a4ad466d8af1aacd1a9 100644 (file)
--- a/arch/arm/mach-tegra/tegra11_clocks.c
+++ b/arch/arm/mach-tegra/tegra11_clocks.c
@@ -1853,7 +1853,7 @@ static void tegra11_utmi_param_configure(struct clk *c)
           ports are assigned to USB2 */
        reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
        reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
-       reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
+       reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
        clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0);
 
        udelay(1);