ALSA: hda: powergate HDA when clock gating

Use powergating APIs to ensure that HDA and display play nice.
Export powergate APIs so snd-intel-hda can be built as a module.

Bug 1178366

Change-Id: I30559b9288fcbd86615a674756e70f04c9fb5d83
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/169245
Reviewed-by: Automatic_Commit_Validation_User

diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index c60503354abefd12f1166b88e6ed9f3ccdbb6e13..d64a5f65636cd3692b0164f92a40cc0e769bdd45 100644 (file)
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -1208,6 +1208,7 @@ err_power:
        return ret;
 #endif
 }
+EXPORT_SYMBOL(tegra_unpowergate_partition);
 
 int tegra_cpu_powergate_id(int cpuid)
 {
@@ -1570,6 +1571,7 @@ err_clk_off:
        return ret;
 #endif
 }
+EXPORT_SYMBOL(tegra_powergate_partition);
 
 int tegra_powergate_partition_with_clk_off(int id)
 {

diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index a45efd3b18f12e72c6d4ca50a915b163e4b64042..e65988de33301cd71c24d1d553b51f5e82a8b17f 100644 (file)
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -67,6 +67,9 @@
 #ifdef CONFIG_SND_HDA_VPR
 #include <linux/nvmap.h>
 #endif
+#ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
+#include <mach/powergate.h>
+#endif
 
 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
@@ -1512,10 +1515,17 @@ static void azx_platform_enable_clocks(struct azx *chip)
 {
        int i;
 
+#ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
+#if defined(CONFIG_ARCH_TEGRA_11x_SOC)
+       tegra_unpowergate_partition(TEGRA_POWERGATE_DISB);
+#endif
+#endif
+
        for (i = 0; i < chip->platform_clk_count; i++)
                clk_enable(chip->platform_clks[i]);
 
        chip->platform_clk_enable++;
+
 }
 
 static void azx_platform_disable_clocks(struct azx *chip)
@@ -1528,6 +1538,12 @@ static void azx_platform_disable_clocks(struct azx *chip)
        for (i = 0; i < chip->platform_clk_count; i++)
                clk_disable(chip->platform_clks[i]);
 
+#ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
+#if defined(CONFIG_ARCH_TEGRA_11x_SOC)
+       tegra_powergate_partition(TEGRA_POWERGATE_DISB);
+#endif
+#endif
+
        chip->platform_clk_enable--;
 }
 #endif /* CONFIG_SND_HDA_PLATFORM_DRIVER */