--- /dev/null
+/*
+ * Copyright (c) 2014-2015 NVIDIA CORPORATION. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <dt-bindings/clk/tegra210-clk.h>
+
+/ {
+ clock {
+ t210-clk-init-table {
+ compatible = "nvidia,tegra-clk-init-table";
+ clkinit-0 = <
+ /* clock id parent id rate ctrl flags */
+ TEGRA210_CLK_ID_HDA TEGRA210_CLK_ID_PLL_P 108000000 0
+ TEGRA210_CLK_ID_HDA2CODEC_2X TEGRA210_CLK_ID_PLL_P 48000000 0
+ TEGRA210_CLK_ID_PWM TEGRA210_CLK_ID_PLL_P 48000000 0
+ TEGRA210_CLK_ID_I2S0 TEGRA210_CLK_ID_PLL_A_OUT0 12288000 0
+ TEGRA210_CLK_ID_I2S1 TEGRA210_CLK_ID_PLL_A_OUT0 0 0
+ TEGRA210_CLK_ID_I2S3 TEGRA210_CLK_ID_PLL_A_OUT0 0 0
+ TEGRA210_CLK_ID_I2S4 TEGRA210_CLK_ID_PLL_A_OUT0 0 0
+ TEGRA210_CLK_ID_SPDIF_OUT TEGRA210_CLK_ID_PLL_A_OUT0 6144000 0
+ TEGRA210_CLK_ID_SPDIF_IN TEGRA210_CLK_ID_PLL_P 48000000 0
+ TEGRA210_CLK_ID_AHUB TEGRA210_CLK_ID_PLL_A_OUT0 12288000 0
+ TEGRA210_CLK_ID_AUDIO1 TEGRA210_CLK_ID_I2S1_SYNC 0 0
+ TEGRA210_CLK_ID_AUDIO3 TEGRA210_CLK_ID_I2S3_SYNC 0 0
+ TEGRA210_CLK_ID_VI_SENSOR TEGRA210_CLK_ID_PLL_P 150000000 0
+ TEGRA210_CLK_ID_VI_SENSOR2 TEGRA210_CLK_ID_PLL_P 150000000 0
+ TEGRA210_CLK_ID_CILAB TEGRA210_CLK_ID_PLL_P 150000000 0
+ TEGRA210_CLK_ID_CILCD TEGRA210_CLK_ID_PLL_P 150000000 0
+ TEGRA210_CLK_ID_CILE TEGRA210_CLK_ID_PLL_P 150000000 0
+ TEGRA210_CLK_ID_EXTERN3 TEGRA210_CLK_ID_PLL_P 41000000 0
+ TEGRA210_CLK_ID_CLK_OUT_3 TEGRA210_CLK_ID_EXTERN3 0 0
+ TEGRA210_CLK_ID_I2C1 TEGRA210_CLK_ID_PLL_P 3200000 0
+ TEGRA210_CLK_ID_I2C2 TEGRA210_CLK_ID_PLL_P 3200000 0
+ TEGRA210_CLK_ID_I2C3 TEGRA210_CLK_ID_PLL_P 3200000 0
+ TEGRA210_CLK_ID_I2C4 TEGRA210_CLK_ID_PLL_P 3200000 0
+ TEGRA210_CLK_ID_I2C5 TEGRA210_CLK_ID_PLL_P 3200000 0
+ TEGRA210_CLK_ID_VII2C TEGRA210_CLK_ID_PLL_P 204000000 0
+ TEGRA210_CLK_ID_I2CSLOW TEGRA210_CLK_ID_CLK_M 1000000 0
+ TEGRA210_CLK_ID_SBC1 TEGRA210_CLK_ID_PLL_P 25000000 0
+ TEGRA210_CLK_ID_SBC2 TEGRA210_CLK_ID_PLL_P 25000000 0
+ TEGRA210_CLK_ID_SBC3 TEGRA210_CLK_ID_PLL_P 25000000 0
+ TEGRA210_CLK_ID_SBC4 TEGRA210_CLK_ID_PLL_P 25000000 0
+ TEGRA210_CLK_ID_QSPI TEGRA210_CLK_ID_PLL_P 133000000 0
+ TEGRA210_CLK_ID_UARTA TEGRA210_CLK_ID_PLL_P 408000000 1
+ TEGRA210_CLK_ID_UARTB TEGRA210_CLK_ID_PLL_P 408000000 0
+ TEGRA210_CLK_ID_UARTC TEGRA210_CLK_ID_PLL_P 408000000 0
+ TEGRA210_CLK_ID_UARTD TEGRA210_CLK_ID_PLL_P 408000000 0
+ TEGRA210_CLK_ID_EXTERN2 TEGRA210_CLK_ID_PLL_P 41000000 0
+ TEGRA210_CLK_ID_CLK_OUT_2 TEGRA210_CLK_ID_EXTERN2 40800000 0
+ TEGRA210_CLK_ID_EXTERN1 TEGRA210_CLK_ID_CLK_M 19200000 1
+ TEGRA210_CLK_ID_CLK_OUT_1 TEGRA210_CLK_ID_EXTERN1 19200000 1
+ TEGRA210_CLK_ID_UART_MIPI_CAL TEGRA210_CLK_ID_PLL_P 68000000 0
+ 0 >;
+ };
+ };
+};
static struct nvadsp_platform_data nvadsp_plat_data;
#endif
-static __initdata struct tegra_clk_init_table t210ref_clk_init_table[] = {
- /* name parent rate enabled */
- { "hda", "pll_p", 108000000, false},
- { "hda2codec_2x", "pll_p", 48000000, false},
- { "pwm", "pll_p", 48000000, false},
- { "i2s0", "pll_a_out0", 12288000, false},
- { "i2s1", "pll_a_out0", 0, false},
- { "i2s3", "pll_a_out0", 0, false},
- { "i2s4", "pll_a_out0", 0, false},
- { "spdif_out", "pll_a_out0", 6144000, false},
- { "spdif_in", "pll_p", 48000000, false},
- { "d_audio", "pll_a_out0", 12288000, false},
- { "audio1", "i2s1_sync", 0, false},
- { "audio3", "i2s3_sync", 0, false},
- { "vi_sensor", "pll_p", 150000000, false},
- { "vi_sensor2", "pll_p", 150000000, false},
- { "cilab", "pll_p", 150000000, false},
- { "cilcd", "pll_p", 150000000, false},
- { "cile", "pll_p", 150000000, false},
- { "extern3", "pll_p", 41000000, false},
- { "clk_out_3", "extern3", 0, false},
- { "i2c1", "pll_p", 3200000, false},
- { "i2c2", "pll_p", 3200000, false},
- { "i2c3", "pll_p", 3200000, false},
- { "i2c4", "pll_p", 3200000, false},
- { "i2c5", "pll_p", 3200000, false},
- { "vii2c", "pll_p", 204000000, false},
- { "i2cslow", "clk_m", 1000000, false},
- { "sbc1", "pll_p", 25000000, false},
- { "sbc2", "pll_p", 25000000, false},
- { "sbc3", "pll_p", 25000000, false},
- { "sbc4", "pll_p", 25000000, false},
- { "qspi", "pll_p", 133000000, false},
- { "uarta", "pll_p", 408000000, true},
- { "uartb", "pll_p", 408000000, false},
- { "uartc", "pll_p", 408000000, false},
- { "uartd", "pll_p", 408000000, false},
- { "extern2", "pll_p", 41000000, false},
- { "clk_out_2", "extern2", 40800000, false},
- { "extern1", "clk_m", 19200000, true},
- { "clk_out_1", "extern1", 19200000, true},
- { "uart_mipi_cal", "pll_p", 68000000, false},
- { NULL, NULL, 0, 0},
-};
-
static void t210ref_usb_init(void)
{
int usb_port_owner_info = tegra_get_usb_port_owner_info();
static void __init tegra_t210ref_early_init(void)
{
if (!tegra_platform_is_fpga()) {
- tegra_clk_init_from_table(t210ref_clk_init_table);
+ tegra_clk_init_from_dt("t210-clk-init-table");
tegra_clk_verify_parents();
}
if (of_machine_is_compatible("nvidia,e2141"))
projects / sojka / nv-tegra / linux-3.10.git / commitdiff