tegra21: dvfs: Integrate CPU DVFS table p4v58

Bug 1558421

Change-Id: Iee5e8e1a616da2346fb6aba683b607828b2242a6
Reviewed-on: http://git-master/r/926679
(cherry picked from commit 926b3b96a5bfd54d1527cc788e4cd1b8cfd87b98)
Signed-off-by: Ishwarya Balaji Gururajan <igururajan@nvidia.com>
Reviewed-on: http://git-master/r/928845
Reviewed-by: Kerwin Wan <kerwinw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hayden Du <haydend@nvidia.com>

diff --git a/drivers/platform/tegra/tegra21_dvfs.c b/drivers/platform/tegra/tegra21_dvfs.c
index ba9f33cc69bce0afc373c64f7c4b3380971d2239..dcc1acbc04d945a3f6ca008fab0a3dec50fd762d 100644 (file)
--- a/drivers/platform/tegra/tegra21_dvfs.c
+++ b/drivers/platform/tegra/tegra21_dvfs.c
@@ -93,7 +93,7 @@ static struct dvfs_rail tegra21_dvfs_rail_vdd_cpu = {
        .stats = {
                .bin_uV = 6250, /* 6.25mV */
        },
-       .version = "p4v57_p4Av07",
+       .version = "p4v58_p4Av07",
 };
 
 static struct dvfs_rail tegra21_dvfs_rail_vdd_core = {
@@ -269,7 +269,100 @@ static struct dvfs_relationship tegra21_dvfs_relationships[] = {
                { 0,       { }, { }, }, \
        }
 
+#define CPU_CVB_TABLE_EUCM2_JOINT_RAIL \
+       .freqs_mult = KHZ,      \
+       .speedo_scale = 100,    \
+       .voltage_scale = 1000,  \
+       .cvb_table = {          \
+               /* f      dfll:    c0,       c1,       c2    pll:    c0,       c1,       c2 */   \
+               {  204000, {  742283 ,        0,        0 }, {        0,        0,        0 } }, \
+               {  306000, {  776249 ,        0,        0 }, {        0,        0,        0 } }, \
+               {  408000, {  810215 ,        0,        0 }, {        0,        0,        0 } }, \
+               {  510000, {  844181 ,        0,        0 }, {        0,        0,        0 } }, \
+               {  612000, {  878147 ,        0,        0 }, {        0,        0,        0 } }, \
+               {  714000, {  912113 ,        0,        0 }, {        0,        0,        0 } }, \
+               {  816000, {  946079 ,        0,        0 }, {        0,        0,        0 } }, \
+               {  918000, {  980045 ,        0,        0 }, {        0,        0,        0 } }, \
+               { 1020000, {  1014011,        0,        0 }, { -2875621,   358099,    -8585 } }, \
+               { 1122000, {  1047977,        0,        0 }, {   -52225,   104159,    -2816 } }, \
+               { 1224000, {  1081943,        0,        0 }, {  1076868,     8356,     -727 } }, \
+               { 1326000, {  1090000,        0,        0 }, {  2208191,   -84659,     1240 } }, \
+               { 1479000, {  1090000,        0,        0 }, {  2519460,  -105063,     1611 } }, \
+               { 1504500, {  1120000,        0,        0 }, {  2639809,  -108729,     1626 } }, \
+               { 0,       { }, { }, }, \
+       }
+
 static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = {
+       {
+               .speedo_id = 10,
+               .process_id = 0,
+               .dfll_tune_data  = {
+                       .tune0          = 0xFFEAD0FF,
+                       .tune0_high_mv  = 0xFFEAD0FF,
+                       .tune_high_min_millivolts = 864,
+                       .tune1          = 0x020091D9,
+                       .droop_rate_min = 1000000,
+                       .min_millivolts = 840,
+               },
+               .pll_tune_data = {
+                       .min_millivolts = 950,
+               },
+               .max_mv = 1120,
+               .max_freq = 1504500,
+               CPU_CVB_TABLE_EUCM2_JOINT_RAIL,
+       },
+       {
+               .speedo_id = 10,
+               .process_id = 1,
+               .dfll_tune_data  = {
+                       .tune0          = 0xFFEAD0FF,
+                       .tune0_high_mv  = 0xFFEAD0FF,
+                       .tune_high_min_millivolts = 864,
+                       .tune1          = 0x025501D0,
+                       .droop_rate_min = 1000000,
+                       .min_millivolts = 840,
+               },
+               .pll_tune_data = {
+                       .min_millivolts = 950,
+               },
+               .max_mv = 1120,
+               .max_freq = 1504500,
+               CPU_CVB_TABLE_EUCM2_JOINT_RAIL,
+       },
+
+       {
+               .speedo_id = 9,
+               .process_id = 0,
+               .dfll_tune_data  = {
+                       .tune0          = 0xFFEAD0FF,
+                       .tune1          = 0x020091D9,
+                       .droop_rate_min = 1000000,
+                       .min_millivolts = 900,
+               },
+               .pll_tune_data = {
+                       .min_millivolts = 950,
+               },
+               .max_mv = 1162,
+               .max_freq = 1555500,
+               CPU_CVB_TABLE_EUCM2,
+       },
+       {
+               .speedo_id = 9,
+               .process_id = 1,
+               .dfll_tune_data  = {
+                       .tune0          = 0xFFEAD0FF,
+                       .tune1          = 0x025501D0,
+                       .droop_rate_min = 1000000,
+                       .min_millivolts = 900,
+               },
+               .pll_tune_data = {
+                       .min_millivolts = 950,
+               },
+               .max_mv = 1162,
+               .max_freq = 1555500,
+               CPU_CVB_TABLE_EUCM2,
+       },
+
        {
                .speedo_id = 8,
                .process_id = 0,

diff --git a/drivers/platform/tegra/tegra21_speedo.c b/drivers/platform/tegra/tegra21_speedo.c
index 0b4b5bbd8fefabd6644863fa8d5409fc644a677c..a9978697389c0d7a52593b602dc6dcf8153d6289 100644 (file)
--- a/drivers/platform/tegra/tegra21_speedo.c
+++ b/drivers/platform/tegra/tegra21_speedo.c
@@ -102,6 +102,7 @@ static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
 
 static void rev_sku_to_speedo_ids(int rev, int sku, int speedo_rev)
 {
+       bool joint_xpu_rail = false;
        bool always_on = false;
        bool shield_sku = false;
        bool vcm31_sku = false;
@@ -109,6 +110,8 @@ static void rev_sku_to_speedo_ids(int rev, int sku, int speedo_rev)
        bool a02 = rev == TEGRA_REVISION_A02;
 
 #ifdef CONFIG_OF
+       joint_xpu_rail = of_property_read_bool(of_chosen,
+                                         "nvidia,tegra-joint_xpu_rail");
        always_on = of_property_read_bool(of_chosen,
                                          "nvidia,tegra-always-on-personality");
        shield_sku = of_property_read_bool(of_chosen,
@@ -180,17 +183,21 @@ static void rev_sku_to_speedo_ids(int rev, int sku, int speedo_rev)
                }
                /* fall thru for a01 part */
        case 0x8F:
-               if (a02) {
-                       cpu_speedo_id = 1;
+               if (a02 && always_on) {
+                       cpu_speedo_id = joint_xpu_rail ? 10 : 9;
                        soc_speedo_id = 0;
                        gpu_speedo_id = 2;
                        threshold_index = 0;
                        core_min_mv = 800;
                        break;
                }
-               /* fall thru for a01 part */
+               /* fall thru for a01 part or not always on */
        default:
-               pr_warn("Tegra21: Unknown SKU %d\n", sku);
+               pr_warn("Tegra21: Unknown SKU/mode:\n");
+               pr_warn("sku = 0x%X a02 = %d shield_sku = %d vcm31_sku = %d\n",
+                       sku, a02, shield_sku, vcm31_sku);
+               pr_warn("joint_xpu_rail = %d always_on = %d\n",
+                       joint_xpu_rail, always_on);
                cpu_speedo_id = 0;
                soc_speedo_id = 0;
                gpu_speedo_id = 0;