}
if (ch) {
- verbose = gk20a_fifo_set_ctx_mmu_error(g, ch);
if (ch->in_use) {
/* disable the channel from hw and increment
* syncpoints */
/* handled during channel free */
g->fifo.deferred_reset_pending = true;
- }
+ } else
+ verbose = gk20a_fifo_set_ctx_mmu_error(g, ch);
+
} else if (f.inst_ptr ==
g->mm.bar1.inst_block.cpu_pa) {
nvhost_err(dev_from_gk20a(g), "mmu fault from bar1");
struct fifo_gk20a *f = &g->fifo;
struct channel_gk20a *ch = &f->channel[isr_data.chid];
- gk20a_set_error_notifier(ch->hwctx,
- NVHOST_CHANNEL_GR_ERROR_SW_NOTIFY);
-
nvhost_dbg(dbg_intr | dbg_gpu_dbg, "exception %08x\n", exception);
if (exception & gr_exception_fe_m()) {
gk20a_gr_clear_sm_hww(g, global_esr);
}
+ if (need_reset)
+ gk20a_set_error_notifier(ch,
+ NVHOST_CHANNEL_GR_ERROR_SW_NOTIFY);
}
gk20a_writel(g, gr_intr_r(), gr_intr_exception_reset_f());