ARM: tegra: clock: Add disabled divisor change option

Added an optional peripheral clocks property that allows to change
divisor value while clock is disabled. Currently no clock on any Tegra
architecture has this property set.

Change-Id: I3b668f19ed94b95f47ed4a8354e63e6a74b6ebd5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/367525
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 554713a06ad7fd15c9f6d27287eb552f625bdb4d..799dd1f63a1572f07bf4bb6a4b6930b972154b67 100644 (file)
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -545,8 +545,8 @@ int clk_set_rate_locked(struct clk *c, unsigned long rate)
         * at given voltage. To guarantee h/w switch to the new setting
         * enable clock while setting rate.
         */
-       if ((c->refcnt == 0) && (c->flags & (DIV_U71 | DIV_U16)) &&
-               clk_is_auto_dvfs(c)) {
+       if ((c->refcnt == 0) && (c->flags & PERIPH_DIV) &&
+               clk_is_auto_dvfs(c) && !clk_can_set_disabled_div(c)) {
                pr_debug("Setting rate of clock %s with refcnt 0\n", c->name);
                ret = clk_enable_locked(c);
                if (ret)
@@ -992,6 +992,19 @@ void __init tegra_clk_verify_parents(void)
        mutex_unlock(&clock_list_lock);
 }
 
+void __init tegra_clk_set_disabled_div_all(void)
+{
+       struct clk *c;
+
+       mutex_lock(&clock_list_lock);
+
+       list_for_each_entry(c, &clocks, node) {
+               if (c->flags & PERIPH_DIV)
+                       c->set_disabled_div = true;
+       }
+       mutex_unlock(&clock_list_lock);
+}
+
 static bool tegra_keep_boot_clocks = false;
 static int __init tegra_keep_boot_clocks_setup(char *__unused)
 {

diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index 6ded1d827aaedf0a6df162d6835e0d3b4ae0923b..84629e542053f7e18bab531f5fee8ce39ad4d7c6 100644 (file)
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -173,6 +173,7 @@ struct clk {
        unsigned long           min_rate;
        bool                    auto_dvfs;
        bool                    cansleep;
+       bool                    set_disabled_div;
        u32                     flags;
        const char              *name;
 
@@ -363,6 +364,7 @@ void tegra_init_max_rate(struct clk *c, unsigned long max_rate);
 void tegra_clk_preset_emc_monitor(unsigned long rate);
 void tegra_periph_clk_safe_rate_init(struct clk *c);
 void tegra_clk_verify_parents(void);
+void tegra_clk_set_disabled_div_all(void);
 void clk_init(struct clk *clk);
 unsigned long tegra_clk_measure_input_freq(void);
 unsigned long clk_get_rate_locked(struct clk *c);
@@ -431,6 +433,11 @@ static inline bool clk_cansleep(struct clk *c)
        return c->cansleep;
 }
 
+static inline bool clk_can_set_disabled_div(struct clk *c)
+{
+       return c->set_disabled_div;
+}
+
 static inline void clk_lock_save(struct clk *c, unsigned long *flags)
 {
        if (clk_cansleep(c)) {