ARM: tegra13: dvfs: Set CPU DFLL tuning parameters

On Tegra13 A02 silicon set CPU DFLL tuning parameters as a function
of chip speed.

Bug 1492902
Bug 1442659

Change-Id: I03a5a419c60ffa86a360c58222b93279f25e3145
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/402656
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

diff --git a/arch/arm/mach-tegra/tegra13_dvfs.c b/arch/arm/mach-tegra/tegra13_dvfs.c
index c1d3a59ff1ad87057a473656dd0ec14dc8479c90..36bf7946c7c143b77a29a00facbabb40c5088a4d 100644 (file)
--- a/arch/arm/mach-tegra/tegra13_dvfs.c
+++ b/arch/arm/mach-tegra/tegra13_dvfs.c
@@ -226,8 +226,6 @@ static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = {
                .speedo_id = 1,
                .process_id = -1,
                .dfll_tune_data  = {
-                       .tune0          = 0x00FF15FF,
-                       .tune0_high_mv  = 0x008040FF,
                        .tune1          = 0x000000FF,
                        .droop_rate_min = 1000000,
                        .tune_high_min_millivolts = 900,
@@ -730,6 +728,19 @@ static int round_voltage(int mv, struct rail_alignment *align, bool up)
        return mv;
 }
 
+static void __init set_cpu_dfll_tuning_data(struct cpu_cvb_dvfs *d, int speedo)
+{
+       if (d->speedo_id == 1) {
+               if (speedo <= 2336) {
+                       d->dfll_tune_data.tune0 = 0x9315FF;
+                       d->dfll_tune_data.tune0_high_mv = 0x9340FF;
+               } else {
+                       d->dfll_tune_data.tune0 = 0x8315FF;
+                       d->dfll_tune_data.tune0_high_mv = 0x8340FF;
+               }
+       }
+}
+
 static int __init set_cpu_dvfs_data(unsigned long max_freq,
        struct cpu_cvb_dvfs *d, struct dvfs *cpu_dvfs, int *max_freq_index)
 {
@@ -741,6 +752,8 @@ static int __init set_cpu_dvfs_data(unsigned long max_freq,
        int speedo = tegra_cpu_speedo_value();
        struct rail_alignment *align = &tegra13_dvfs_rail_vdd_cpu.alignment;
 
+       set_cpu_dfll_tuning_data(d, speedo);
+
        min_dfll_mv = d->dfll_tune_data.min_millivolts;
        min_dfll_mv =  round_voltage(min_dfll_mv, align, true);
        d->max_mv = round_voltage(d->max_mv, align, false);