ARM: tegra12: clock: Disable VDE clock during init on Si

Change-Id: I811d13e4a5ac4fa852e69d4391234f2fc5584f49
Signed-off-by: Somasundaram S <somasundaram@nvidia.com>
Reviewed-on: http://git-master/r/263386
Tested-by: Somu Sundaram <somasundarams@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 873087ac08372bc515bea701a9518f90314e741e..99e597f03820ae240e0ecab541177d709d9af8ec 100644 (file)
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -409,6 +409,8 @@ static __initdata struct tegra_clk_init_table tegra12x_clk_init_table[] = {
                TEGRA_CLK_INIT_PLATFORM_NON_SI },
        { "cl_dvfs_soc", "clk_m",       13000000,       false,
                TEGRA_CLK_INIT_PLATFORM_NON_SI },
+       { "vde",        "pll_c3",       48400000,       true,
+               TEGRA_CLK_INIT_CPU_ASIM},
 #endif
 #ifdef CONFIG_TEGRA_SLOW_CSITE
        { "csite",      "clk_m",        1000000,        true },
@@ -440,8 +442,6 @@ static __initdata struct tegra_clk_init_table tegra12x_clk_init_table[] = {
        { "soc_therm",  "pll_p",        51000000,       false },
        { "tsensor",    "clk_m",        500000,         false },
 #endif
-       { "vde",        "pll_c3",       48400000,       true,
-               TEGRA_CLK_INIT_CPU_ASIM},
        { NULL,         NULL,           0,              0},
 };
 static __initdata struct tegra_clk_init_table tegra12x_cbus_init_table[] = {