arm: tegra12: initialize pll_a_out0

Before initializing i2s clock we need to intialize
its parent clocks pll_a_out0

Bug 200027051

Change-Id: I9fa42e82bbf3c7742a57ffc698c31e6ca1d94bd5
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/496028
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bryan Wu <pengw@nvidia.com>
Tested-by: Bryan Wu <pengw@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

diff --git a/arch/arm/mach-tegra/board-ardbeg.c b/arch/arm/mach-tegra/board-ardbeg.c
index d2f727a8d239a879bd4a5a828622553038d7c887..20c49fd46aeec25a6f2051c48343c3e990def544 100644 (file)
--- a/arch/arm/mach-tegra/board-ardbeg.c
+++ b/arch/arm/mach-tegra/board-ardbeg.c
@@ -171,6 +171,7 @@ static __initdata struct tegra_clk_init_table ardbeg_clk_init_table[] = {
        { "hda2codec_2x", "pll_p",      48000000,       false},
        { "pwm",        "pll_p",        48000000,       false},
        { "pll_a",      "pll_p_out1",   282240000,      false},
+       { "pll_a_out0", "pll_a",        12288000,       false},
        { "i2s1",       "pll_a_out0",   0,              false},
        { "i2s3",       "pll_a_out0",   0,              false},
        { "i2s4",       "pll_a_out0",   0,              false},