clock tegra21: Update SBUS and CBUS round rate

- Added threshold between SBUS low and high source PLL rate ranges
  into round table if bus DVFS is not installed to match SBUS possible
  rates when DVFS is present.

- Allowed CBUS minimum rate to be equal to maximum rate to support
  single point DVFS table.

Change-Id: I4de077eedaf23ea3f6d098ac3b146b62fc25cfef
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/723077
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

diff --git a/drivers/platform/tegra/tegra21_clocks.c b/drivers/platform/tegra/tegra21_clocks.c
index eadd7f9cc9fdc66f926b0d6fd290956720895257..fdea05ae658e8f593334a0879361e59e65a99b61 100644 (file)
--- a/drivers/platform/tegra/tegra21_clocks.c
+++ b/drivers/platform/tegra/tegra21_clocks.c
@@ -1874,8 +1874,8 @@ static void sbus_build_round_table(struct clk *c)
        if (!c->dvfs || !c->dvfs->num_freqs) {
                sbus_build_round_table_one(
                        c, sclk_pclk_unity_ratio_rate_max, j++);
-               sbus_build_round_table_one(
-                       c, c->max_rate, j++);
+               sbus_build_round_table_one(c, threshold, j++);
+               sbus_build_round_table_one(c, c->max_rate, j++);
                sbus_round_table_size = j;
                return;
        }
@@ -5679,7 +5679,7 @@ static long tegra21_clk_cbus_round_updown(struct clk *c, unsigned long rate,
        /* update min now, since no dvfs table was available during init
           (skip placeholder entries set to 1 kHz) */
        if (!c->min_rate) {
-               for (i = 0; i < (c->dvfs->num_freqs - 1); i++) {
+               for (i = 0; i < c->dvfs->num_freqs; i++) {
                        if (c->dvfs->freqs[i] > 1 * c->dvfs->freqs_mult) {
                                c->min_rate = c->dvfs->freqs[i];
                                break;