gpu: nvgpu: gm20b: use jiffies for wait on PMU

bug 200153970
bug 1707442

Change-Id: Ia5f616269bfeb834540bf4da6ecfc6e399682819
Reviewed-on: http://git-master/r/836966
(cherry picked from commit 9bc019e3b62984b3d1f12da5edc3221ee44a86b1)
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/841356
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Rajkumar Kasirajan <rkasirajan@nvidia.com>
Tested-by: Rajkumar Kasirajan <rkasirajan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
index ecb0f8ab7b20cb155e77ef8b720d1e87c1ee7902..21ad21ae0111063dfa5b7981e23a6ea04dbb2361 100644 (file)
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
@@ -1227,7 +1227,7 @@ int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt)
        gm20b_init_pmu_setup_hw1(g, desc, acr->hsbl_ucode.size);
        /* Poll for HALT */
        if (b_wait_for_halt) {
-               err = pmu_wait_for_halt(g, gk20a_get_gr_idle_timeout(g));
+               err = pmu_wait_for_halt(g, ACR_COMPLETION_TIMEOUT_MS);
                if (err == 0) {
                        /* Clear the HALT interrupt */
                  if (clear_halt_interrupt_status(g, gk20a_get_gr_idle_timeout(g)))
@@ -1257,40 +1257,51 @@ err_done:
 /*!
 *      Wait for PMU to halt
 *      @param[in]      g               GPU object pointer
-*      @param[in]      timeout_us      Timeout in Us for PMU to halt
+*      @param[in]      timeout         Timeout in msec for PMU to halt
 *      @return '0' if PMU halts
 */
 int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout)
 {
        u32 data = 0;
-       while (timeout != 0) {
+       int completion = -EBUSY;
+       unsigned long end_jiffies = jiffies + msecs_to_jiffies(timeout);
+
+       while (time_before(jiffies, end_jiffies) ||
+                       !tegra_platform_is_silicon()) {
                data = gk20a_readl(g, pwr_falcon_cpuctl_r());
-               if (data & pwr_falcon_cpuctl_halt_intr_m())
+               if (data & pwr_falcon_cpuctl_halt_intr_m()) {
                        /*CPU is halted break*/
+                       completion = 0;
                        break;
-               timeout--;
+               }
                udelay(1);
        }
-       if (timeout == 0)
-               return -EBUSY;
-       data = gk20a_readl(g, pwr_falcon_mailbox0_r());
-       if (data) {
-               gk20a_err(dev_from_gk20a(g), "ACR boot failed, err %x", data);
-               return -EAGAIN;
+       if (completion)
+               gk20a_err(dev_from_gk20a(g), "ACR boot timed out");
+       else {
+               data = gk20a_readl(g, pwr_falcon_mailbox0_r());
+               if (data) {
+                       gk20a_err(dev_from_gk20a(g),
+                               "ACR boot failed, err %x", data);
+                       completion = -EAGAIN;
+               }
        }
-       return 0;
+       return completion;
 }
 
 /*!
 *      Wait for PMU halt interrupt status to be cleared
 *      @param[in]      g               GPU object pointer
-*      @param[in]      timeout_us      Timeout in Us for PMU to halt
+*      @param[in]      timeout_us      Timeout in msec for halt to clear
 *      @return '0' if PMU halt irq status is clear
 */
 int clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout)
 {
        u32 data = 0;
-       while (timeout != 0) {
+       unsigned long end_jiffies = jiffies + msecs_to_jiffies(timeout);
+
+       while (time_before(jiffies, end_jiffies) ||
+                       !tegra_platform_is_silicon()) {
                gk20a_writel(g, pwr_falcon_irqsclr_r(),
                             gk20a_readl(g, pwr_falcon_irqsclr_r()) | (0x10));
                data = gk20a_readl(g, (pwr_falcon_irqstat_r()));

diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
index d26f91ffc907c4e903a5105b4650c7d791ce46bf..3b83cf3da284a288a7f1d35e3614130516851058 100644 (file)
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
@@ -19,6 +19,7 @@
 #include "mm_gm20b.h"
 
 /*Defines*/
+#define ACR_COMPLETION_TIMEOUT_MS 10000 /*in msec */
 
 /*chip specific defines*/
 #define MAX_SUPPORTED_LSFM 2 /*PMU, FECS, GPCCS*/