arm: tegra12: disable MC Holdoff for some clients

Disable MC Holdoff for HYST_VDETPER, HYST_VDEMCER, HYST_VDEMBER,
HYST_VDEBSEVR, HYST_MSENCSRD, HYST_ISPRAB, HYST_ISPRA, HYST_VICSRD
Correct some incorrect clients name definitions

Bug 1440582

Change-Id: I0b50668218051a060062b565f82e45abff82d875
Signed-off-by: Terry Wang <terwang@nvidia.com>
Reviewed-on: http://git-master/r/369254
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

diff --git a/arch/arm/mach-tegra/tegra12_emc.c b/arch/arm/mach-tegra/tegra12_emc.c
index 7405d60dc541581c65a6647693f48f3e5b02c78e..2f5fb9720f75c2268aa2ccdb35921f6b432c35a5 100644 (file)
--- a/arch/arm/mach-tegra/tegra12_emc.c
+++ b/arch/arm/mach-tegra/tegra12_emc.c
@@ -1518,18 +1518,17 @@ module_param_cb(pasr_enable, &tegra12_pasr_enable_ops, &pasr_enable, 0644);
 
 void tegra12_mc_holdoff_enable(void)
 {
-       mc_writel(HYST_MSENCSRD | HYST_DISPLAYHCB | HYST_DISPLAYHC |
-               HYST_DISPLAY0CB | HYST_DISPLAY0C | YST_DISPLAY0BB |
-               YST_DISPLAY0B | YST_DISPLAY0AB | YST_DISPLAY0A,
+       mc_writel(HYST_DISPLAYHCB | HYST_DISPLAYHC |
+               HYST_DISPLAY0CB | HYST_DISPLAY0C | HYST_DISPLAY0BB |
+               HYST_DISPLAY0B | HYST_DISPLAY0AB | HYST_DISPLAY0A,
                MC_EMEM_ARB_HYSTERESIS_0_0);
-       mc_writel(HYST_VDEDBGW | HYST_VDEBSEVW | HYST_MSENCSWR |
-               YST_VDETPER | YST_VDEMCER | YST_VDEMBER | YST_VDEBSEVR,
+       mc_writel(HYST_VDEDBGW | HYST_VDEBSEVW | HYST_MSENCSWR,
                MC_EMEM_ARB_HYSTERESIS_1_0);
        mc_writel(HYST_DISPLAYT | HYST_GPUSWR | HYST_ISPWBB |
-               HYST_ISPWAB | HYST_ISPRAB | YST_ISPWB | YST_ISPWA |
-               YST_ISPRA | YST_VDETPMW | YST_VDEMBEW,
+               HYST_ISPWAB | HYST_ISPWB | HYST_ISPWA |
+               HYST_VDETPMW | HYST_VDEMBEW,
                MC_EMEM_ARB_HYSTERESIS_2_0);
-       mc_writel(HYST_DISPLAYD | HYST_VIW | HYST_VICSWR | HYST_VICSRD,
+       mc_writel(HYST_DISPLAYD | HYST_VIW | HYST_VICSWR,
                MC_EMEM_ARB_HYSTERESIS_3_0);
 }
 

diff --git a/arch/arm/mach-tegra/tegra12_emc.h b/arch/arm/mach-tegra/tegra12_emc.h
index e7bd8759fc6f59eb2d2691dfb41dffa8525e2b84..6a65cd208fe1e19a709e491954cbb0f592d70fda 100644 (file)
--- a/arch/arm/mach-tegra/tegra12_emc.h
+++ b/arch/arm/mach-tegra/tegra12_emc.h
@@ -459,10 +459,10 @@ enum {
 #define HYST_AFIR                              (0x1 << 14)
 #define HYST_DISPLAY0CB                                (0x1 << 6)
 #define HYST_DISPLAY0C                         (0x1 << 5)
-#define YST_DISPLAY0BB                         (0x1 << 4)
-#define YST_DISPLAY0B                          (0x1 << 3)
-#define YST_DISPLAY0AB                         (0x1 << 2)
-#define YST_DISPLAY0A                          (0x1 << 1)
+#define HYST_DISPLAY0BB                                (0x1 << 4)
+#define HYST_DISPLAY0B                         (0x1 << 3)
+#define HYST_DISPLAY0AB                                (0x1 << 2)
+#define HYST_DISPLAY0A                         (0x1 << 1)
 #define HYST_PTCR                              (0x1 << 0)
 
 #define HYST_VDEDBGW                           (0x1 << 31)
@@ -477,12 +477,12 @@ enum {
 #define HYST_AVPCARM7W                         (0x1 << 18)
 #define HYST_AFIW                              (0x1 << 17)
 #define HYST_MSENCSWR                          (0x1 << 11)
-#define YST_MPCORER                            (0x1 << 7)
-#define YST_MPCORELPR                          (0x1 << 6)
-#define YST_VDETPER                            (0x1 << 5)
-#define YST_VDEMCER                            (0x1 << 4)
-#define YST_VDEMBER                            (0x1 << 3)
-#define YST_VDEBSEVR                           (0x1 << 2)
+#define HYST_MPCORER                           (0x1 << 7)
+#define HYST_MPCORELPR                         (0x1 << 6)
+#define HYST_VDETPER                           (0x1 << 5)
+#define HYST_VDEMCER                           (0x1 << 4)
+#define HYST_VDEMBER                           (0x1 << 3)
+#define HYST_VDEBSEVR                          (0x1 << 2)
 
 #define HYST_DISPLAYT                          (0x1 << 26)
 #define HYST_GPUSWR                            (0x1 << 25)
@@ -498,24 +498,24 @@ enum {
 #define HYST_XUSB_DEVR                         (0x1 << 12)
 #define HYST_XUSB_HOSTW                                (0x1 << 11)
 #define HYST_XUSB_HOSTR                                (0x1 << 10)
-#define YST_ISPWB                              (0x1 << 7)
-#define YST_ISPWA                              (0x1 << 6)
-#define YST_ISPRA                              (0x1 << 4)
-#define YST_VDETPMW                            (0x1 << 1)
-#define YST_VDEMBEW                            (0x1 << 0)
+#define HYST_ISPWB                             (0x1 << 7)
+#define HYST_ISPWA                             (0x1 << 6)
+#define HYST_ISPRA                             (0x1 << 4)
+#define HYST_VDETPMW                           (0x1 << 1)
+#define HYST_VDEMBEW                           (0x1 << 0)
 
 #define HYST_DISPLAYD                          (0x1 << 19)
 #define HYST_VIW                               (0x1 << 18)
 #define HYST_VICSWR                            (0x1 << 13)
 #define HYST_VICSRD                            (0x1 << 12)
-#define YST_SDMMCWAB                           (0x1 << 7)
-#define YST_SDMMCW                             (0x1 << 6)
-#define YST_SDMMCWAA                           (0x1 << 5)
-#define YST_SDMMCWA                            (0x1 << 4)
-#define YST_SDMMCRAB                           (0x1 << 3)
-#define YST_SDMMCR                             (0x1 << 2)
-#define YST_SDMMCRAA                           (0x1 << 1)
-#define YST_SDMMCRA                            (0x1 << 0)
+#define HYST_SDMMCWAB                          (0x1 << 7)
+#define HYST_SDMMCW                            (0x1 << 6)
+#define HYST_SDMMCWAA                          (0x1 << 5)
+#define HYST_SDMMCWA                           (0x1 << 4)
+#define HYST_SDMMCRAB                          (0x1 << 3)
+#define HYST_SDMMCR                            (0x1 << 2)
+#define HYST_SDMMCRAA                          (0x1 << 1)
+#define HYST_SDMMCRA                           (0x1 << 0)
 
 #define MC_DIS_EXTRA_SNAP_LEVELS               0x2ac