]> rtime.felk.cvut.cz Git - sojka/nv-tegra/linux-3.10.git/commitdiff
ARM: tegra: Check VPR before enabling GPU
authorTerje Bergstrom <tbergstrom@nvidia.com>
Mon, 31 Mar 2014 09:37:48 +0000 (12:37 +0300)
committerWinnie Hsu <whsu@nvidia.com>
Thu, 22 May 2014 23:05:01 +0000 (16:05 -0700)
Check that VPR is locked down before enabling GPU.

Change-Id: I455b3cb0fee489e19daf7217f925d7d8348458f1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/390184
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
(cherry picked from commit 9857267dba8b4081a94e90cf39d76f4d4fb2e71e)
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Signed-off-by: Prabhu Kuttiyam <pkuttiyam@nvidia.com>
Reviewed-on: http://git-master/r/408430
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
arch/arm/mach-tegra/powergate-t12x.c

index 05933a731a91fe112558513bfa0b6a21fe09d0ee..14bd096be15eade9aa6215e9f9b04613471acbf4 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -286,6 +286,7 @@ static struct powergate_partition_info tegra12x_powergate_partition_info[] = {
 #define MC_CLIENT_HOTRESET_STAT                0x204
 #define MC_CLIENT_HOTRESET_CTRL_1      0x970
 #define MC_CLIENT_HOTRESET_STAT_1      0x974
+#define MC_VIDEO_PROTECT_REG_CTRL      0x650
 
 #define PMC_GPU_RG_CNTRL_0             0x2d4
 
@@ -444,12 +445,27 @@ err_power_off:
        return ret;
 }
 
+static int mc_check_vpr(void)
+{
+       int ret = 0;
+       u32 val = mc_read(MC_VIDEO_PROTECT_REG_CTRL);
+       if ((val & 1) == 0) {
+               pr_err("VPR configuration not locked down\n");
+               ret = -EINVAL;
+       }
+       return ret;
+}
+
 static int tegra12x_gpu_unpowergate(int id,
        struct powergate_partition_info *pg_info)
 {
        int ret = 0;
        bool first = false;
 
+       ret = mc_check_vpr();
+       if (ret)
+               return ret;
+
        if (!gpu_rail) {
                gpu_rail = tegra_dvfs_get_rail_by_name("vdd_gpu");
                if (IS_ERR_OR_NULL(gpu_rail)) {