tegra: dc: Round up target HDMI rate

Since Tegra Clock Framework rounds down when module clock divider is
determined, rounded up target rate for sor clock switch to compensate.

Bug 200162245

Change-Id: Ic6fde0ebf32143609a399a9f6ed2b6805d9f7029
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/926981
(cherry picked from commit 2dfc8941dc6c64cdf5d888c6c2dc55332d024962)
Reviewed-on: http://git-master/r/927853
Reviewed-by: Aly Hirani <ahirani@nvidia.com>
Tested-by: Aly Hirani <ahirani@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-by: Naveen Kumar S <nkumars@nvidia.com>

diff --git a/drivers/video/tegra/dc/hdmi2.0.c b/drivers/video/tegra/dc/hdmi2.0.c
index 1a2a5f95a843b3667ef47d0b7f1d47f2342f8c8e..8f0079f72c05beacff6a339a23152def9acc2dc3 100644 (file)
--- a/drivers/video/tegra/dc/hdmi2.0.c
+++ b/drivers/video/tegra/dc/hdmi2.0.c
@@ -1887,8 +1887,8 @@ static void tegra_hdmi_config_clk(struct tegra_hdmi *hdmi, u32 clk_type)
                        clk_get_rate(clk_get_parent(sor->src_switch_clk));
 
                /* Set sor divider */
-               if (rate != parent_rate / div) {
-                       rate = parent_rate / div;
+               if (rate != DIV_ROUND_UP(parent_rate, div)) {
+                       rate = DIV_ROUND_UP(parent_rate, div);
                        clk_set_rate(sor->src_switch_clk, rate);
                }