clock: tegra21: Fix PLLM/B parent specification

Changed PLLM/B parent from PLL reference clock to oscillator.

PLL reference clock is a divided version of oscillator clock. Although
the divisor on Tegra21 is set 1:1 and PLL parent rate is not changing
by this commit, the clock tree topology is fixed.

Bug 1632849

Change-Id: I7713a640bf0b0099dff3ec4aaf4c7886bb236bf6
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/728201
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

diff --git a/drivers/platform/tegra/tegra21_clocks.c b/drivers/platform/tegra/tegra21_clocks.c
index fa2d0aab27bdb448a086a03ad1b5e1855a541eab..275fb44cece710c777913dc4f43207523775f7ed 100644 (file)
--- a/drivers/platform/tegra/tegra21_clocks.c
+++ b/drivers/platform/tegra/tegra21_clocks.c
@@ -7336,7 +7336,7 @@ static struct clk tegra_pll_m = {
        .flags     = PLLM,
        .ops       = &tegra_pllm_ops,
        .reg       = 0x90,
-       .parent    = &tegra_pll_ref,
+       .parent    = &tegra_clk_osc,
        .max_rate  = 1866000000,
        .u.pll = {
                .input_min = 9600000,
@@ -7368,7 +7368,7 @@ static struct clk tegra_pll_mb = {
        .clk_id    = TEGRA210_CLK_ID_PLL_MB,
        .ops       = &tegra_pllmb_ops,
        .reg       = 0x5e8,
-       .parent    = &tegra_pll_ref,
+       .parent    = &tegra_clk_osc,
        .max_rate  = 1866000000,
        .u.pll = {
                .input_min = 9600000,