PCIE: tegra: resume timing correction

The time from +1.05V_RUN to PEX_L1_RST_L signal
(PEX_L1_RST_N on T124) should be 100ms minimum

Bug 1500840

Change-Id: I170ed3225f80b5ef0ccaf4b38565d3adf94a674a
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/402841
(cherry picked from commit d380528e5e865437681c21befc40de430b39f9a9)
Reviewed-on: http://git-master/r/404966
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 292871e0a56564684331e30966699d35c0e542e9..808292c30514972686393053561a8e49b67b340d 100644 (file)
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -2355,6 +2355,8 @@ static int tegra_pcie_resume_noirq(struct device *dev)
                        return ret;
                }
        }
+       /* give 100ms for 1.05v to come up */
+       msleep(100);
        ret = tegra_pcie_power_on();
        if (ret) {
                pr_err("PCIE: Failed to power on: %d\n", ret);