Change VRR native mode location from mode list index
VRR_NATIVE_MODE_IDX to the last mode in the list. This
matches bootloader behavior.
Bug
1645593
Change-Id: I79f17c80d846cc236b0dd8c8f4874c2daf863894
Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-on: http://git-master/r/744705
(cherry picked from commit
860c86538feb0febace6305510e894580f1176c2)
Reviewed-on: http://git-master/r/751050
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>
Required properties:
- name: Should be "display-timings"
- Child nodes represent modes. Several modes can be prepared. For VRR panels, the panel's native mode
- must be placed in index VRR_NATIVE_MODE_IDX (value 1, i.e. second mode in the list, as of the writing
- of this comment).
+ must be placed in the last index
1.A.i.x) NVIDIA Display Controller Mode timing
This must be contained in display-timings parent node. This contains mode settings, including
Required properties:
- name: Should be "display-timings"
- Child nodes represent modes. Several modes can be prepared. For VRR panels, the panel's native mode
- must be placed in index VRR_NATIVE_MODE_IDX (value 1, i.e. second mode in the list, as of the writing
- of this comment).
+ must be placed in the last index
1.A.i.x) NVIDIA Display Controller Mode timing
This must be contained in display-timings parent node. This contains mode settings, including
Required properties:
- name: Should be "display-timings"
- Child nodes represent modes. Several modes can be prepared. For VRR panels, the panel's native mode
- must be placed in index VRR_NATIVE_MODE_IDX (value 1, i.e. second mode in the list, as of the writing
- of this comment).
+ must be placed in the last index
1.A.i.x) NVIDIA Display Controller Mode timing
This must be contained in display-timings parent node. This contains mode settings, including
if (!vrr) return;
- m = &dc->out->modes[VRR_NATIVE_MODE_IDX];
+ m = &dc->out->modes[dc->out->n_modes-1];
vrr->v_front_porch = m->v_front_porch;
vrr->v_back_porch = m->v_back_porch;
vrr->pclk = m->pclk;
dc->initialized = true;
} else if (out->n_modes > 0) {
/* For VRR panels, default mode is first in the list,
- * and native panel mode is at index VRR_NATIVE_MODE_IDX.
+ * and native panel mode is the last.
* Initialization must occur using the native panel mode. */
if (dc->out->vrr) {
tegra_dc_set_mode(dc,
- &dc->out->modes[VRR_NATIVE_MODE_IDX]);
+ &dc->out->modes[dc->out->n_modes-1]);
tegra_dc_setup_vrr(dc);
} else
tegra_dc_set_mode(dc, &dc->out->modes[0]);
(dc->out->hotplug_gpio >= 0 || \
dc->out->type == TEGRA_DC_OUT_DP) : 0)
-#define VRR_NATIVE_MODE_IDX 1
-
static inline int tegra_dc_io_start(struct tegra_dc *dc)
{
int ret = 0;
mode->v_ref_to_sync = 1;
} else if (dc->out->vrr) {
mode->h_ref_to_sync =
- dc->out->modes[VRR_NATIVE_MODE_IDX].h_ref_to_sync;
+ dc->out->modes[dc->out->n_modes-1].h_ref_to_sync;
mode->v_ref_to_sync =
- dc->out->modes[VRR_NATIVE_MODE_IDX].v_ref_to_sync;
+ dc->out->modes[dc->out->n_modes-1].v_ref_to_sync;
} else {
calc_ref_to_sync(mode);
}