arm64: tegra: enable both ports of pcie

Bug 200044360

Change-Id: Ie9db8b74750a122ce289665d11e8f5ca377ddb18
Signed-off-by: Shreshtha SAHU <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/595897
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

diff --git a/arch/arm64/boot/dts/tegra210-jetson-e-p2595-0000-a00-00.dts b/arch/arm64/boot/dts/tegra210-jetson-e-p2595-0000-a00-00.dts
index cf7506afc59029d317270b531207f77fb5a23038..f3de17c6e119d4ab9c8f001a29666a774a4b7d4a 100644 (file)
--- a/arch/arm64/boot/dts/tegra210-jetson-e-p2595-0000-a00-00.dts
+++ b/arch/arm64/boot/dts/tegra210-jetson-e-p2595-0000-a00-00.dts
@@ -147,6 +147,37 @@
                };
        };
 
+       pcie-controller {
+               nvidia,wake-gpio = <&gpio TEGRA_GPIO(A, 2) 0>;
+               nvidia,lane-map = <0x14>;
+               dvdd-pex-pll-supply = <&max77620_ldo1>;
+               l0-dvddio-pex-supply = <&max77620_ldo1>;
+               l1-dvddio-pex-supply = <&max77620_ldo1>;
+               l2-dvddio-pex-supply = <&max77620_ldo1>;
+               l3-dvddio-pex-supply = <&max77620_ldo1>;
+               l4-dvddio-pex-supply = <&max77620_ldo1>;
+               l5-dvddio-pex-supply = <&max77620_ldo1>;
+               l6-dvddio-pex-supply = <&max77620_ldo1>;
+               hvdd-pex-pll-e-supply = <&max77620_sd3>;
+               l0-hvddio-pex-supply = <&max77620_sd3>;
+               l1-hvddio-pex-supply = <&max77620_sd3>;
+               l2-hvddio-pex-supply = <&max77620_sd3>;
+               l3-hvddio-pex-supply = <&max77620_sd3>;
+               l4-hvddio-pex-supply = <&max77620_sd3>;
+               l5-hvddio-pex-supply = <&max77620_sd3>;
+               l6-hvddio-pex-supply = <&max77620_sd3>;
+               vddio-pex-ctl-supply = <&max77620_sd3>;
+               status = "okay";
+
+               pci@1,0 {
+                       status = "okay";
+               };
+
+               pci@2,0 {
+                       status = "okay";
+               };
+       };
+
        host1x {
                /* tegradc.0 */
                dc@54200000 {