* When emc_clock is set through TEGRA_CAMERA_EMC_CLK,
* info->rate has peak memory bandwidth in Bps.
*/
- unsigned long bw = info->rate >> 10;
+ unsigned long bw = info->rate / 1000;
#ifdef CONFIG_ARCH_TEGRA_11x_SOC
int ret = 0;
#endif
- clk_set_rate(clk, tegra_emc_bw_to_freq_req(bw) << 10);
- dev_dbg(camera->dev, "%s: bw=%lu, emc_clk=%d\n",
- __func__, bw,
- tegra_emc_bw_to_freq_req(bw) << 10);
+ dev_dbg(camera->dev, "%s: bw=%lu\n",
+ __func__, bw);
+
+#ifdef CONFIG_ARCH_TEGRA_11x_SOC
+ /*
+ * Take into account iso client efficiency here until
+ * isomgr is alive. It's 35%.
+ */
+ clk_set_rate(clk,
+ ((100*tegra_emc_bw_to_freq_req(bw)) / 35) * 1000);
+#else
+ clk_set_rate(clk, tegra_emc_bw_to_freq_req(bw) * 1000);
+#endif
+
#ifdef CONFIG_ARCH_TEGRA_11x_SOC
/*
* There is no way to figure out what latency