]> rtime.felk.cvut.cz Git - sojka/nv-tegra/linux-3.10.git/commitdiff
video: tegra: host: pod: change vic freq tuning
authorArun Kannan <akannan@nvidia.com>
Tue, 12 May 2015 00:15:45 +0000 (17:15 -0700)
committerMatthew Pedro <mapedro@nvidia.com>
Mon, 1 Jun 2015 21:49:59 +0000 (14:49 -0700)
Tune nvhost_podgov scaling algo params for
vic03 frequency scaling.

Bug 1640539

Change-Id: Id5583b5cd60d6b4449470d8c3df1e5d06bc4aedb
Signed-off-by: Arun Kannan <akannan@nvidia.com>
Reviewed-on: http://git-master/r/741438
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Kamal Balagopalan <kbalagopalan@nvidia.com>
Reviewed-by: Ming Wong <miwong@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
drivers/video/tegra/host/pod_scaling.c

index 64898950bab58a66d6c244a775d4cd6da5ec7bc6..7ece923321eb1ed543b3aed7da3c7e2953d4b2ad 100644 (file)
@@ -3,7 +3,7 @@
  *
  * Tegra Graphics Host 3D clock scaling
  *
- * Copyright (c) 2012-2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2012-2015, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -839,15 +839,15 @@ static int nvhost_pod_init(struct devfreq *df)
        podgov->p_use_throughput_hint = 1;
 
        if (!strcmp(d->name, "vic03.0")) {
-               podgov->p_load_max = 990;
-               podgov->p_load_target = 800;
+               podgov->p_load_max = 100;
+               podgov->p_load_target = 10;
                podgov->p_bias = 80;
                podgov->p_hint_lo_limit = 500;
                podgov->p_hint_hi_limit = 997;
                podgov->p_scaleup_limit = 1100;
                podgov->p_scaledown_limit = 1300;
-               podgov->p_smooth = 10;
-               podgov->p_damp = 7;
+               podgov->p_smooth = 30;
+               podgov->p_damp = 9;
        } else {
                switch (cid) {
                case TEGRA_CHIPID_TEGRA14: