ARM: tegra12: clock: Unify fixed source bus round ops

Unified round operations for shared buses with fixed rate sources:
1x_bus and sbus complex.

Change-Id: I191814346e90f19cac3cf52bee3c5d831eed641d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/379748
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

diff --git a/arch/arm/mach-tegra/tegra12_clocks.c b/arch/arm/mach-tegra/tegra12_clocks.c
index f027e15de2602872dcad67a06abfc673c004d411..b12ad7fba25754dfcdd1922747c24b5f4ebd63cc 100644 (file)
--- a/arch/arm/mach-tegra/tegra12_clocks.c
+++ b/arch/arm/mach-tegra/tegra12_clocks.c
@@ -866,6 +866,31 @@ static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
        return divider_u16 - 1;
 }
 
+static long fixed_src_bus_round_updown(struct clk *c, struct clk *src,
+                                      u32 flags, unsigned long rate, bool up)
+{
+       int divider;
+       unsigned long source_rate, round_rate;
+
+       source_rate = clk_get_rate(src);
+
+       divider = clk_div71_get_divider(source_rate, rate + (up ? -1 : 1),
+               flags, up ? ROUND_DIVIDER_DOWN : ROUND_DIVIDER_UP);
+       if (divider < 0)
+               return c->min_rate;
+
+       round_rate = source_rate * 2 / (divider + 2);
+
+       if (round_rate > c->max_rate) {
+               divider += flags & DIV_U71_INT ? 2 : 1;
+#if !DIVIDER_1_5_ALLOWED
+               divider = max(2, divider);
+#endif
+               round_rate = source_rate * 2 / (divider + 2);
+       }
+       return round_rate;
+}
+
 static inline bool bus_user_is_slower(struct clk *a, struct clk *b)
 {
        return a->u.shared_bus_user.client->max_rate * a->div <
@@ -1987,32 +2012,16 @@ static void tegra12_sbus_cmplx_init(struct clk *c)
 static long tegra12_sbus_cmplx_round_updown(struct clk *c, unsigned long rate,
                                            bool up)
 {
-       int divider;
-       unsigned long source_rate, round_rate;
+       unsigned long round_rate;
        struct clk *new_parent;
 
        rate = max(rate, c->min_rate);
 
        new_parent = (rate <= c->u.system.threshold) ?
                c->u.system.sclk_low : c->u.system.sclk_high;
-       source_rate = clk_get_rate(new_parent->parent);
-
-       divider = clk_div71_get_divider(source_rate, rate,
-               new_parent->flags, up ? ROUND_DIVIDER_DOWN : ROUND_DIVIDER_UP);
-       if (divider < 0)
-               return c->min_rate;
 
-       if (divider == 1)
-               divider = 0;
-
-       round_rate = source_rate * 2 / (divider + 2);
-       if (round_rate > c->max_rate) {
-               divider += new_parent->flags & DIV_U71_INT ? 2 : 1;
-#if !DIVIDER_1_5_ALLOWED
-               divider = max(2, divider);
-#endif
-               round_rate = source_rate * 2 / (divider + 2);
-       }
+       round_rate = fixed_src_bus_round_updown(
+               c, new_parent->parent, new_parent->flags, rate, up);
 
        if (new_parent == c->u.system.sclk_high) {
                /* Prevent oscillation across threshold */
@@ -4947,27 +4956,7 @@ static struct clk_ops tegra_periph_clk_ops = {
 static long _1x_round_updown(struct clk *c, struct clk *src,
                             unsigned long rate, bool up)
 {
-       int divider;
-       unsigned long source_rate, round_rate;
-
-       source_rate = clk_get_rate(src);
-
-       divider = clk_div71_get_divider(source_rate, rate + (up ? -1 : 1),
-               c->flags, up ? ROUND_DIVIDER_DOWN : ROUND_DIVIDER_UP);
-
-       if (divider < 0)
-               return c->min_rate;
-
-       round_rate = source_rate * 2 / (divider + 2);
-
-       if (round_rate > c->max_rate) {
-               divider += c->flags & DIV_U71_INT ? 2 : 1;
-#if !DIVIDER_1_5_ALLOWED
-               divider = max(2, divider);
-#endif
-               round_rate = source_rate * 2 / (divider + 2);
-       }
-       return round_rate;
+       return fixed_src_bus_round_updown(c, src, c->flags, rate, up);
 }
 
 static long tegra12_1xbus_round_updown(struct clk *c, unsigned long rate,