ARM: tegra13: clock: Rename CPU super clock ops

Renamed CPU super clock mux operations from tegra13_cpu_clk_* to
tegra13_super_cclk_* (cpu_clk_* operations are separate, shared
by tegra12 and tegra13 and existing naming was confusing).

Updated several comments.

Change-Id: I88049f3a4c8eb5ee465fc293f7d77d95a5e387a0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/373330
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

diff --git a/arch/arm/mach-tegra/tegra12_clocks.c b/arch/arm/mach-tegra/tegra12_clocks.c
index dc7e5ff36ec281e026942e8054f8726299706c21..57ece0f777f1c96982693060ee18a9ef0d2c8ba8 100644 (file)
--- a/arch/arm/mach-tegra/tegra12_clocks.c
+++ b/arch/arm/mach-tegra/tegra12_clocks.c
@@ -1081,7 +1081,7 @@ static int tegra12_super_clk_enable(struct clk *c)
 
 static void tegra12_super_clk_disable(struct clk *c)
 {
-       /* since tegra 3 has 2 CPU super clocks - low power lp-mode clock and
+       /* since tegra12 has 2 CPU super clocks - low power lp-mode clock and
           geared up g-mode super clock - mode switch may request to disable
           either of them; accept request with no affect on h/w */
 }
@@ -1205,7 +1205,7 @@ static struct clk_ops tegra_super_ops = {
 };
 
 #ifdef CONFIG_ARCH_TEGRA_13x_SOC
-static void tegra13_cpu_clk_init(struct clk *c)
+static void tegra13_super_cclk_init(struct clk *c)
 {
        u32 val;
        int source;
@@ -1241,19 +1241,18 @@ static void tegra13_cpu_clk_init(struct clk *c)
                clk13_writel(0, c->reg + SUPER_CLK_DIVIDER);
 }
 
-static int tegra13_cpu_clk_enable(struct clk *c)
+static int tegra13_super_cclk_enable(struct clk *c)
 {
        return 0;
 }
 
-static void tegra13_cpu_clk_disable(struct clk *c)
+static void tegra13_super_cclk_disable(struct clk *c)
 {
-       /* since tegra 3 has 2 CPU super clocks - low power lp-mode clock and
-          geared up g-mode super clock - mode switch may request to disable
-          either of them; accept request with no affect on h/w */
+       /* since tegra13 has 1 CPU super clocks that is never disabled
+          by clock framework accept request with no affect on h/w */
 }
 
-static int tegra13_cpu_clk_set_parent(struct clk *c, struct clk *p)
+static int tegra13_super_cclk_set_parent(struct clk *c, struct clk *p)
 {
        u32 val;
        const struct clk_mux_sel *sel;
@@ -1294,9 +1293,9 @@ static int tegra13_cpu_clk_set_parent(struct clk *c, struct clk *p)
  * other children, otherwise the rate will change underneath the other
  * children.
  */
-static int tegra13_cpu_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra13_super_cclk_set_rate(struct clk *c, unsigned long rate)
 {
-       /* In tegra12_cpu_clk_set_plls() and  tegra12_sbus_cmplx_set_rate()
+       /* In tegra12_cpu_clk_set_plls() op (shared with tegra13 as well)
         * this call is skipped by directly setting rate of source plls. If we
         * ever use 7.1 divider at other than 1:1 setting, or exercise s/w
         * skipper control, not only this function, but cpu and sbus set_rate
@@ -1305,12 +1304,12 @@ static int tegra13_cpu_clk_set_rate(struct clk *c, unsigned long rate)
        return clk_set_rate(c->parent, rate);
 }
 
-static struct clk_ops tegra13_cpu_ops = {
-       .init                   = tegra13_cpu_clk_init,
-       .enable                 = tegra13_cpu_clk_enable,
-       .disable                = tegra13_cpu_clk_disable,
-       .set_parent             = tegra13_cpu_clk_set_parent,
-       .set_rate               = tegra13_cpu_clk_set_rate,
+static struct clk_ops tegra13_super_cclk_ops = {
+       .init                   = tegra13_super_cclk_init,
+       .enable                 = tegra13_super_cclk_enable,
+       .disable                = tegra13_super_cclk_disable,
+       .set_parent             = tegra13_super_cclk_set_parent,
+       .set_rate               = tegra13_super_cclk_set_rate,
 };
 #endif
 
@@ -1333,9 +1332,13 @@ static int tegra12_cpu_clk_enable(struct clk *c)
 
 static void tegra12_cpu_clk_disable(struct clk *c)
 {
-       /* since tegra 3 has 2 virtual CPU clocks - low power lp-mode clock
-          and geared up g-mode clock - mode switch may request to disable
-          either of them; accept request with no affect on h/w */
+       /*
+        * tegra12 has 2 virtual CPU clocks - low power lp-mode clock
+        * and geared up g-mode clock - mode switch may request to disable
+        * either of them; tegra13 that shares CPU ops with tegra12 has
+        * only one virtual CPU that is never disabled; in any case accept
+        * request with no affect on h/w/
+        */
 }
 
 static int tegra12_cpu_clk_set_plls(struct clk *c, unsigned long rate,
@@ -7420,8 +7423,7 @@ static struct clk tegra_clk_cclk_g = {
        .flags  = DIV_U71 | DIV_U71_INT | MUX,
        .inputs = mux_cclk_g,
        .reg    = 0x20,
-       /*.ops  = &tegra_super_ops,*/
-       .ops    = &tegra13_cpu_ops,
+       .ops    = &tegra13_super_cclk_ops,
        .max_rate = 3000000000UL,
 };