video: tegra: dc: support all formats on T124

Change-Id: I4f138daa014d8d688a74205658b94d4c904f4823
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/280874
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Xue Dong <xdong@nvidia.com>
Reviewed-by: Wen Yi <wyi@nvidia.com>
Tested-by: Wen Yi <wyi@nvidia.com>
(cherry picked from commit 1aebf628c0ea2cb3d62c07a0d20587f16db132fa)
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>

diff --git a/drivers/video/tegra/dc/dc_config.c b/drivers/video/tegra/dc/dc_config.c
index 8b9e0c638d904128fe32a9890b34af9097a941a0..9a9bac97fe00c501ed895508c0861ee2a9df2134 100644 (file)
--- a/drivers/video/tegra/dc/dc_config.c
+++ b/drivers/video/tegra/dc/dc_config.c
@@ -223,7 +223,8 @@ struct tegra_dc_feature t114_feature_table_b = {
 };
 
 static struct tegra_dc_feature_entry t124_feature_entries_a[] = {
-       { 0, TEGRA_DC_FEATURE_FORMATS, {TEGRA_WIN_FMT_BASE,} },
+       { 0, TEGRA_DC_FEATURE_FORMATS,
+                       { TEGRA_WIN_FMT_BASE, TEGRA_WIN_FMT_T124_HIGH } },
        { 0, TEGRA_DC_FEATURE_BLEND_TYPE, {2,} },
        { 0, TEGRA_DC_FEATURE_MAXIMUM_SIZE, {4096, 1, 4096, 1,} },
        { 0, TEGRA_DC_FEATURE_MAXIMUM_SCALE, {2, 2, 2, 2,} },
@@ -232,7 +233,8 @@ static struct tegra_dc_feature_entry t124_feature_entries_a[] = {
        { 0, TEGRA_DC_FEATURE_INVERT_TYPE, {1, 1, 0,} },
        { 0, TEGRA_DC_FEATURE_FIELD_TYPE, {1,} },
 
-       { 1, TEGRA_DC_FEATURE_FORMATS, {TEGRA_WIN_FMT_BASE,} },
+       { 1, TEGRA_DC_FEATURE_FORMATS,
+                       { TEGRA_WIN_FMT_BASE, TEGRA_WIN_FMT_T124_HIGH } },
        { 1, TEGRA_DC_FEATURE_BLEND_TYPE, {2,} },
        { 1, TEGRA_DC_FEATURE_MAXIMUM_SIZE, {4096, 1, 4096, 1,} },
        { 1, TEGRA_DC_FEATURE_MAXIMUM_SCALE, {2, 2, 2, 2,} },
@@ -241,7 +243,8 @@ static struct tegra_dc_feature_entry t124_feature_entries_a[] = {
        { 1, TEGRA_DC_FEATURE_INVERT_TYPE, {1, 1, 0,} },
        { 1, TEGRA_DC_FEATURE_FIELD_TYPE, {1,} },
 
-       { 2, TEGRA_DC_FEATURE_FORMATS, {TEGRA_WIN_FMT_BASE,} },
+       { 2, TEGRA_DC_FEATURE_FORMATS,
+                       { TEGRA_WIN_FMT_BASE, TEGRA_WIN_FMT_T124_HIGH } },
        { 2, TEGRA_DC_FEATURE_BLEND_TYPE, {2,} },
        { 2, TEGRA_DC_FEATURE_MAXIMUM_SIZE, {4096, 1, 4096, 1,} },
        { 2, TEGRA_DC_FEATURE_MAXIMUM_SCALE, {2, 2, 2, 2,} },
@@ -261,7 +264,8 @@ static struct tegra_dc_feature_entry t124_feature_entries_a[] = {
 };
 
 static struct tegra_dc_feature_entry t124_feature_entries_b[] = {
-       { 0, TEGRA_DC_FEATURE_FORMATS, {TEGRA_WIN_FMT_BASE,} },
+       { 0, TEGRA_DC_FEATURE_FORMATS,
+                       { TEGRA_WIN_FMT_BASE, TEGRA_WIN_FMT_T124_HIGH } },
        { 0, TEGRA_DC_FEATURE_BLEND_TYPE, {2,} },
        { 0, TEGRA_DC_FEATURE_MAXIMUM_SIZE, {4096, 1, 4096, 1,} },
        { 0, TEGRA_DC_FEATURE_MAXIMUM_SCALE, {2, 2, 2, 2,} },
@@ -270,7 +274,8 @@ static struct tegra_dc_feature_entry t124_feature_entries_b[] = {
        { 0, TEGRA_DC_FEATURE_INVERT_TYPE, {1, 1, 0,} },
        { 0, TEGRA_DC_FEATURE_FIELD_TYPE, {1,} },
 
-       { 1, TEGRA_DC_FEATURE_FORMATS, {TEGRA_WIN_FMT_BASE,} },
+       { 1, TEGRA_DC_FEATURE_FORMATS,
+                       { TEGRA_WIN_FMT_BASE, TEGRA_WIN_FMT_T124_HIGH } },
        { 1, TEGRA_DC_FEATURE_BLEND_TYPE, {2,} },
        { 1, TEGRA_DC_FEATURE_MAXIMUM_SIZE, {4096, 1, 4096, 1,} },
        { 1, TEGRA_DC_FEATURE_MAXIMUM_SCALE, {2, 2, 2, 2,} },
@@ -279,7 +284,8 @@ static struct tegra_dc_feature_entry t124_feature_entries_b[] = {
        { 1, TEGRA_DC_FEATURE_INVERT_TYPE, {1, 1, 0,} },
        { 1, TEGRA_DC_FEATURE_FIELD_TYPE, {1,} },
 
-       { 2, TEGRA_DC_FEATURE_FORMATS, {TEGRA_WIN_FMT_BASE,} },
+       { 2, TEGRA_DC_FEATURE_FORMATS,
+                       { TEGRA_WIN_FMT_BASE, TEGRA_WIN_FMT_T124_HIGH } },
        { 2, TEGRA_DC_FEATURE_BLEND_TYPE, {2,} },
        { 2, TEGRA_DC_FEATURE_MAXIMUM_SIZE, {4096, 1, 4096, 1,} },
        { 2, TEGRA_DC_FEATURE_MAXIMUM_SCALE, {2, 2, 2, 2,} },

diff --git a/drivers/video/tegra/dc/dc_config.h b/drivers/video/tegra/dc/dc_config.h
index c51ba4604456e43cebd4e8365bde3831cc31b389..a0818302e807cc29afb150a4807cab8a336b1ba6 100644 (file)
--- a/drivers/video/tegra/dc/dc_config.h
+++ b/drivers/video/tegra/dc/dc_config.h
@@ -28,60 +28,81 @@
 
 #define ENTRY_SIZE     4       /* Size of feature entry args */
 
+/* adjust large bit shift for an individual 32-bit word */
+#define BIT_FOR_WORD(word, x) ( \
+               (x) >= (word) * 32 && \
+               (x) < 32 + (word) * 32 \
+               ? BIT((x) - 32) : 0)
+#define HIGHBIT(x) BIT_FOR_WORD(1, x)
+#define LOWBIT(x) BIT_FOR_WORD(0, x)
+
 /* Define the supported formats. TEGRA_WIN_FMT_WIN_x macros are defined
  * based on T20/T30 formats. */
-#define TEGRA_WIN_FMT_BASE_CNT (TEGRA_WIN_FMT_YUV422RA + 1)
-#define TEGRA_WIN_FMT_BASE     ((1 << TEGRA_WIN_FMT_P8) | \
-                               (1 << TEGRA_WIN_FMT_B4G4R4A4) | \
-                               (1 << TEGRA_WIN_FMT_B5G5R5A) | \
-                               (1 << TEGRA_WIN_FMT_B5G6R5) | \
-                               (1 << TEGRA_WIN_FMT_AB5G5R5) | \
-                               (1 << TEGRA_WIN_FMT_B8G8R8A8) | \
-                               (1 << TEGRA_WIN_FMT_R8G8B8A8) | \
-                               (1 << TEGRA_WIN_FMT_YCbCr422) | \
-                               (1 << TEGRA_WIN_FMT_YUV422) | \
-                               (1 << TEGRA_WIN_FMT_YCbCr420P) | \
-                               (1 << TEGRA_WIN_FMT_YUV420P) | \
-                               (1 << TEGRA_WIN_FMT_YCbCr422P) | \
-                               (1 << TEGRA_WIN_FMT_YUV422P) | \
-                               (1 << TEGRA_WIN_FMT_YCbCr422R) | \
-                               (1 << TEGRA_WIN_FMT_YUV422R))
-
-#define TEGRA_WIN_FMT_WIN_A    ((1 << TEGRA_WIN_FMT_P1) | \
-                               (1 << TEGRA_WIN_FMT_P2) | \
-                               (1 << TEGRA_WIN_FMT_P4) | \
-                               (1 << TEGRA_WIN_FMT_P8) | \
-                               (1 << TEGRA_WIN_FMT_B4G4R4A4) | \
-                               (1 << TEGRA_WIN_FMT_B5G5R5A) | \
-                               (1 << TEGRA_WIN_FMT_B5G6R5) | \
-                               (1 << TEGRA_WIN_FMT_AB5G5R5) | \
-                               (1 << TEGRA_WIN_FMT_B8G8R8A8) | \
-                               (1 << TEGRA_WIN_FMT_R8G8B8A8) | \
-                               (1 << TEGRA_WIN_FMT_B6x2G6x2R6x2A8) | \
-                               (1 << TEGRA_WIN_FMT_R6x2G6x2B6x2A8))
+#define TEGRA_WIN_FMT_BASE     (BIT(TEGRA_WIN_FMT_P8) | \
+                               BIT(TEGRA_WIN_FMT_B4G4R4A4) | \
+                               BIT(TEGRA_WIN_FMT_B5G5R5A) | \
+                               BIT(TEGRA_WIN_FMT_B5G6R5) | \
+                               BIT(TEGRA_WIN_FMT_AB5G5R5) | \
+                               BIT(TEGRA_WIN_FMT_B8G8R8A8) | \
+                               BIT(TEGRA_WIN_FMT_R8G8B8A8) | \
+                               BIT(TEGRA_WIN_FMT_YCbCr422) | \
+                               BIT(TEGRA_WIN_FMT_YUV422) | \
+                               BIT(TEGRA_WIN_FMT_YCbCr420P) | \
+                               BIT(TEGRA_WIN_FMT_YUV420P) | \
+                               BIT(TEGRA_WIN_FMT_YCbCr422P) | \
+                               BIT(TEGRA_WIN_FMT_YUV422P) | \
+                               BIT(TEGRA_WIN_FMT_YCbCr422R) | \
+                               BIT(TEGRA_WIN_FMT_YUV422R))
+
+#define TEGRA_WIN_FMT_T124_LOW TEGRA_WIN_FMT_BASE
+#define TEGRA_WIN_FMT_T124_HIGH  (HIGHBIT(TEGRA_DC_EXT_FMT_YCbCr444P) | \
+                               HIGHBIT(TEGRA_DC_EXT_FMT_YUV444P) | \
+                               HIGHBIT(TEGRA_DC_EXT_FMT_YCrCb420SP) | \
+                               HIGHBIT(TEGRA_DC_EXT_FMT_YCbCr420SP) | \
+                               HIGHBIT(TEGRA_DC_EXT_FMT_YCrCb422SP) | \
+                               HIGHBIT(TEGRA_DC_EXT_FMT_YCbCr422SP) | \
+                               HIGHBIT(TEGRA_DC_EXT_FMT_YVU420SP) | \
+                               HIGHBIT(TEGRA_DC_EXT_FMT_YUV420SP) | \
+                               HIGHBIT(TEGRA_DC_EXT_FMT_YVU422SP) | \
+                               HIGHBIT(TEGRA_DC_EXT_FMT_YUV422SP) | \
+                               HIGHBIT(TEGRA_DC_EXT_FMT_YVU444SP) | \
+                               HIGHBIT(TEGRA_DC_EXT_FMT_YUV444SP))
+
+#define TEGRA_WIN_FMT_WIN_A    (BIT(TEGRA_WIN_FMT_P1) | \
+                               BIT(TEGRA_WIN_FMT_P2) | \
+                               BIT(TEGRA_WIN_FMT_P4) | \
+                               BIT(TEGRA_WIN_FMT_P8) | \
+                               BIT(TEGRA_WIN_FMT_B4G4R4A4) | \
+                               BIT(TEGRA_WIN_FMT_B5G5R5A) | \
+                               BIT(TEGRA_WIN_FMT_B5G6R5) | \
+                               BIT(TEGRA_WIN_FMT_AB5G5R5) | \
+                               BIT(TEGRA_WIN_FMT_B8G8R8A8) | \
+                               BIT(TEGRA_WIN_FMT_R8G8B8A8) | \
+                               BIT(TEGRA_WIN_FMT_B6x2G6x2R6x2A8) | \
+                               BIT(TEGRA_WIN_FMT_R6x2G6x2B6x2A8))
 
 #define TEGRA_WIN_FMT_WIN_B    (TEGRA_WIN_FMT_BASE | \
-                               (1 << TEGRA_WIN_FMT_B6x2G6x2R6x2A8) | \
-                               (1 << TEGRA_WIN_FMT_R6x2G6x2B6x2A8) | \
-                               (1 << TEGRA_WIN_FMT_YCbCr422RA) | \
-                               (1 << TEGRA_WIN_FMT_YUV422RA))
+                               BIT(TEGRA_WIN_FMT_B6x2G6x2R6x2A8) | \
+                               BIT(TEGRA_WIN_FMT_R6x2G6x2B6x2A8) | \
+                               BIT(TEGRA_WIN_FMT_YCbCr422RA) | \
+                               BIT(TEGRA_WIN_FMT_YUV422RA))
 
 #define TEGRA_WIN_FMT_WIN_C    (TEGRA_WIN_FMT_BASE | \
-                               (1 << TEGRA_WIN_FMT_B6x2G6x2R6x2A8) | \
-                               (1 << TEGRA_WIN_FMT_R6x2G6x2B6x2A8) | \
-                               (1 << TEGRA_WIN_FMT_YCbCr422RA) | \
-                               (1 << TEGRA_WIN_FMT_YUV422RA))
+                               BIT(TEGRA_WIN_FMT_B6x2G6x2R6x2A8) | \
+                               BIT(TEGRA_WIN_FMT_R6x2G6x2B6x2A8) | \
+                               BIT(TEGRA_WIN_FMT_YCbCr422RA) | \
+                               BIT(TEGRA_WIN_FMT_YUV422RA))
 
 /* preferred formats do not include 32-bpp formats */
 #define TEGRA_WIN_PREF_FMT_WIN_B       (TEGRA_WIN_FMT_WIN_B & \
-                               ~(1 << TEGRA_WIN_FMT_B8G8R8A8) & \
-                               ~(1 << TEGRA_WIN_FMT_R8G8B8A8))
-
-#define TEGRA_WIN_FMT_SIMPLE   ((1 << TEGRA_WIN_FMT_B4G4R4A4) | \
-                               (1 << TEGRA_WIN_FMT_B5G5R5A) | \
-                               (1 << TEGRA_WIN_FMT_B5G6R5) | \
-                               (1 << TEGRA_WIN_FMT_B8G8R8A8) | \
-                               (1 << TEGRA_WIN_FMT_R8G8B8A8))
+                               ~BIT(TEGRA_WIN_FMT_B8G8R8A8) & \
+                               ~BIT(TEGRA_WIN_FMT_R8G8B8A8))
+
+#define TEGRA_WIN_FMT_SIMPLE   (BIT(TEGRA_WIN_FMT_B4G4R4A4) | \
+                               BIT(TEGRA_WIN_FMT_B5G5R5A) | \
+                               BIT(TEGRA_WIN_FMT_B5G6R5) | \
+                               BIT(TEGRA_WIN_FMT_B8G8R8A8) | \
+                               BIT(TEGRA_WIN_FMT_R8G8B8A8))
 
 
 /* For each entry, we define the offset to read specific feature. Define the