arm: tegra: sysedp: 2nd update of AP+DRAM table for T132

Bug 1469388

Change-Id: I1342e6a0cfdde83ee98163a0cc1080e5cf2e564a
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: http://git-master/r/413157
(cherry picked from commit 047713898790ec89daff11c90675497499ac2428)
Reviewed-on: http://git-master/r/413106
Reviewed-by: Steve Rogers <srogers@nvidia.com>

diff --git a/drivers/platform/tegra/tegra13_edp.c b/drivers/platform/tegra/tegra13_edp.c
index 9976f0c308c4a68290b977a83207b66a220af7d3..1785523ef96d5a7810a1d893b795d41be2fb57e6 100644 (file)
--- a/drivers/platform/tegra/tegra13_edp.c
+++ b/drivers/platform/tegra/tegra13_edp.c
@@ -22,35 +22,35 @@
 static struct tegra_sysedp_corecap t132_sysedp_corecap[] = {
        /*mW     CPU intensive load        GPU intensive load    */
        /*mW     budget  gpu(khz) mem(khz)  budget  gpu(khz) mem(khz) pthrot(mW)*/
-       {5000,  {3000,  180000, 933000}, {3000,  180000, 933000}, 2739 },
-       {6000,  {4000,  180000, 933000}, {3500,  252000, 933000}, 3509 },
-       {7000,  {5000,  180000, 933000}, {3500,  324000, 933000}, 4084 },
-       {8000,  {6000,  252000, 933000}, {3500,  396000, 933000}, 4564 },
-       {9000,  {6000,  180000, 933000}, {3500,  468000, 933000}, 5043 },
-       {10000, {7000,  180000, 933000}, {6000,  396000, 933000}, 5868 },
-       {11000, {7000,  252000, 933000}, {6000,  468000, 933000}, 6348 },
-       {12000, {7000,  396000, 933000}, {6500,  468000, 933000}, 7307 },
-       {13000, {9000,  180000, 933000}, {6000,  540000, 933000}, 7714 },
-       {14000, {10000, 252000, 933000}, {6000,  612000, 933000}, 8835 },
-       {15000, {10000, 324000, 933000}, {6000,  684000, 933000}, 9600 },
-       {16000, {11000, 252000, 933000}, {6000,  708000, 933000}, 9978 },
-       {17000, {12000, 180000, 933000}, {6000,  756000, 933000}, 10434 },
-       {18000, {12000, 324000, 933000}, {7000,  756000, 933000}, 11393 },
-       {19000, {13000, 252000, 933000}, {7000,  804000, 933000}, 11935 },
-       {20000, {13000, 324000, 933000}, {7500,  804000, 933000}, 12414 },
-       {21000, {14000, 252000, 933000}, {6500,  853000, 933000}, 13643 },
-       {22000, {14000, 396000, 933000}, {9000,  853000, 933000}, 14602 },
-       {23000, {15000, 252000, 933000}, {9000,  853000, 933000}, 13643 },
-       {24000, {16000, 180000, 933000}, {9500,  853000, 933000}, 14432 },
-       {25000, {16800, 180000, 933000}, {10000, 853000, 933000}, 15815 },
-       {26000, {16800, 324000, 933000}, {11000, 853000, 933000}, 16774 },
-       {27000, {16800, 468000, 933000}, {11000, 853000, 933000}, 17733 },
-       {28000, {16800, 540000, 933000}, {11500, 853000, 933000}, 18479 },
-       {29000, {16800, 540000, 933000}, {13000, 853000, 933000}, 18479 },
-       {30000, {16800, 648000, 933000}, {13000, 853000, 933000}, 20252 },
-       {31000, {16800, 708000, 933000}, {13500, 853000, 933000}, 21407 },
-       {32000, {16800, 708000, 933000}, {14000, 853000, 933000}, 21407 },
-       {33000, {16800, 756000, 933000}, {14500, 853000, 933000}, 22430 },
+       {5000,  {3000,  180000, 933000}, {3000,  180000, 933000}, 2603 },
+       {6000,  {4000,  180000, 933000}, {3500,  252000, 933000}, 3374 },
+       {7000,  {5000,  180000, 933000}, {3500,  324000, 933000}, 3839 },
+       {8000,  {5000,  252000, 933000}, {3500,  396000, 933000}, 4265 },
+       {9000,  {5000,  396000, 933000}, {3500,  468000, 933000}, 4848 },
+       {10000, {6000,  324000, 933000}, {6000,  324000, 933000}, 5765 },
+       {11000, {7000,  252000, 933000}, {6000,  396000, 933000}, 6158 },
+       {12000, {7000,  396000, 933000}, {6000,  468000, 933000}, 6774 },
+       {13000, {8000,  252000, 933000}, {6000,  540000, 933000}, 6765 },
+       {14000, {10000, 252000, 933000}, {6000,  612000, 933000}, 8490 },
+       {15000, {10000, 324000, 933000}, {6000,  684000, 933000}, 9184 },
+       {16000, {11000, 252000, 933000}, {6000,  708000, 933000}, 9639 },
+       {17000, {11000, 396000, 933000}, {6000,  756000, 933000}, 10507 },
+       {18000, {12000, 324000, 933000}, {7000,  756000, 933000}, 11149 },
+       {19000, {13000, 252000, 933000}, {7000,  804000, 933000}, 11745 },
+       {20000, {13000, 324000, 933000}, {7500,  804000, 933000}, 12170 },
+       {21000, {14000, 252000, 933000}, {6500,  853000, 933000}, 12570 },
+       {22000, {14000, 396000, 933000}, {9000,  853000, 933000}, 13421 },
+       {23000, {15000, 252000, 933000}, {9000,  853000, 933000}, 13453 },
+       {24000, {15000, 396000, 933000}, {9500,  853000, 933000}, 14304 },
+       {25000, {16000, 324000, 933000}, {10000, 853000, 933000}, 15147 },
+       {26000, {16800, 324000, 933000}, {11000, 853000, 933000}, 16530 },
+       {27000, {16800, 468000, 933000}, {11000, 853000, 933000}, 17282 },
+       {28000, {16800, 540000, 933000}, {11500, 853000, 933000}, 17282 },
+       {29000, {16800, 540000, 933000}, {13000, 853000, 933000}, 18400 },
+       {30000, {16800, 648000, 933000}, {13000, 853000, 933000}, 19238 },
+       {31000, {16800, 708000, 933000}, {13500, 853000, 933000}, 20064 },
+       {32000, {16800, 708000, 933000}, {14000, 853000, 933000}, 20064 },
+       {33000, {16800, 756000, 933000}, {14500, 853000, 933000}, 20947 },
 };
 
 struct tegra_sysedp_corecap *tegra_get_sysedp_corecap(unsigned int *sz)