pcie: host: tegra: fix pads2plle powerdown

configures pads2plle powerdown by checking the CLKREQ status
immediately after link is up with end point

Bug 200187688
Bug 200184534

Change-Id: Ic69ca1f249c400d115fbd5a4bc91543780db0b59
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: http://git-master/r/1119022
(cherry picked from commit 33272b966c6fafdf8b43c7e437916887aa5c38db)
Reviewed-on: http://git-master/r/1119633
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 094cfd6e4fb8aca2b2fca7323f45c2559c61e03a..5021b2a4c888a0baf38982c792d6cd6c3e10d7df 100644 (file)
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -1150,7 +1150,6 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
        val |= AFI_PLLE_CONTROL_PCIE2PLLE_CONTROL_EN;
        list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
                if (port->disable_clock_request) {
-                       val |= AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
                        val &= ~AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
                        break;
                }
@@ -2031,6 +2030,21 @@ static void tegra_pcie_update_lane_width(struct tegra_pcie_port *port)
                RP_LINK_CONTROL_STATUS_NEG_LINK_WIDTH) >> 20;
 }
 
+static void tegra_pcie_update_pads2plle(struct tegra_pcie_port *port)
+{
+       unsigned long ctrl = 0;
+       u32 val = 0;
+
+       ctrl = tegra_pcie_port_get_pex_ctrl(port);
+       /* AFI_PEX_STATUS is AFI_PEX_CTRL + 4 */
+       val = afi_readl(port->pcie, ctrl + 4);
+       if (val & 0x1) {
+               val = afi_readl(port->pcie, AFI_PLLE_CONTROL);
+               val &= ~AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
+               afi_writel(port->pcie, val, AFI_PLLE_CONTROL);
+       }
+}
+
 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
 static void mbist_war(struct tegra_pcie *pcie, bool apply)
 {
@@ -2091,6 +2105,7 @@ static void tegra_pcie_check_ports(struct tegra_pcie *pcie)
                        port->status = 1;
                        pcie->num_ports++;
                        tegra_pcie_update_lane_width(port);
+                       tegra_pcie_update_pads2plle(port);
                        continue;
                }
                dev_info(pcie->dev, "link %u down, ignoring\n", port->index);