ARM: dt: tegra: set #iommu-cells to 1

Align iommus= property to what upstream recommends.

Bug 200032393
Bug 200031968

Change-Id: I221595b56b9176349025e88fc73679e88e19f24b
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/496772
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>

diff --git a/arch/arm/boot/dts/tegra124-soc.dtsi b/arch/arm/boot/dts/tegra124-soc.dtsi
index 568c3cca6663ee1cc0b57b195f70f409280f4c68..bed185e485f0a4900d7910eb2d45068415e78f6e 100644 (file)
--- a/arch/arm/boot/dts/tegra124-soc.dtsi
+++ b/arch/arm/boot/dts/tegra124-soc.dtsi
@@ -100,7 +100,7 @@
                       0x0 0x6000c000 0x0 0x1000>;
                #asids = <128>;
                dma-window = <0x0 0x80000000 0x0 0x7ff00000>;
-               #iommu-cells = <3>;
+               #iommu-cells = <1>;
                swgid-mask = <0x1 0xfffecdcf>;
                #num-translation-enable = <4>;
                #num-asid-security = <8>;
@@ -196,7 +196,7 @@
                reg-shift = <2>;
                interrupts = <0 36 0x04>;
                nvidia,dma-request-selector = <&apbdma 8>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                status = "disabled";
                dmas = <&apbdma 8>, <&apbdma 8>;
                dma-names = "rx", "tx";
@@ -208,7 +208,7 @@
                reg-shift = <2>;
                interrupts = <0 37 0x04>;
                nvidia,dma-request-selector = <&apbdma 9>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                status = "disabled";
                dmas = <&apbdma 9>, <&apbdma 9>;
                dma-names = "rx", "tx";
@@ -220,7 +220,7 @@
                reg-shift = <2>;
                interrupts = <0 46 0x04>;
                nvidia,dma-request-selector = <&apbdma 10>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                status = "disabled";
                dmas = <&apbdma 10>, <&apbdma 10>;
                dma-names = "rx", "tx";
@@ -232,7 +232,7 @@
                reg-shift = <2>;
                interrupts = <0 90 0x04>;
                nvidia,dma-request-selector = <&apbdma 19>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                status = "disabled";
                dmas = <&apbdma 19>, <&apbdma 19>;
                dma-names = "rx", "tx";
@@ -253,7 +253,7 @@
                interrupts = <0 38 0x04>;
                scl-gpio = <&gpio 20 0>; /* gpio PC4 */
                sda-gpio = <&gpio 21 0>; /* gpio PC5 */
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                status = "okay";
                clock-frequency = <400000>;
        };
@@ -266,7 +266,7 @@
                interrupts = <0 84 0x04>;
                scl-gpio = <&gpio 157 0>; /* gpio PT5 */
                sda-gpio = <&gpio 158 0>; /* gpio PT6 */
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                status = "okay";
                clock-frequency = <100000>;
        };
@@ -279,7 +279,7 @@
                interrupts = <0 92 0x04>;
                scl-gpio = <&gpio 217 0>; /* gpio PBB1 */
                sda-gpio = <&gpio 218 0>; /* gpio PBB2 */
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                status = "okay";
                clock-frequency = <400000>;
        };
@@ -292,7 +292,7 @@
                interrupts = <0 120 0x04>;
                scl-gpio = <&gpio 172 0>; /* gpio PV4 */
                sda-gpio = <&gpio 173 0>; /* gpio PV5 */
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                status = "okay";
                clock-frequency = <100000>;
        };
@@ -306,7 +306,7 @@
                nvidia,require-cldvfs-clock;
                scl-gpio = <&gpio 206 0>; /* gpio PZ6 */
                sda-gpio = <&gpio 207 0>; /* gpio PZ7 */
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                status = "okay";
                clock-frequency = <400000>;
        };
@@ -317,7 +317,7 @@
                compatible = "nvidia,tegra124-i2c";
                reg = <0x0 0x7000d100 0x0 0x100>;
                interrupts = <0 63 0x04>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                status = "okay";
                clock-frequency = <400000>;
        };
@@ -327,7 +327,7 @@
                reg = <0x0 0x7000d400 0x0 0x200>;
                interrupts = <0 59 0x04>;
                nvidia,dma-request-selector = <&apbdma 15>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                #address-cells = <1>;
                #size-cells = <0>;
                clocks = <&tegra_car 41>;
@@ -341,7 +341,7 @@
                reg = <0x0 0x7000d600 0x0 0x200>;
                interrupts = <0 82 0x04>;
                nvidia,dma-request-selector = <&apbdma 16>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                #address-cells = <1>;
                #size-cells = <0>;
                clocks = <&tegra_car 44>;
@@ -355,7 +355,7 @@
                reg = <0x0 0x7000d800 0x0 0x200>;
                interrupts = <0 83 0x04>;
                nvidia,dma-request-selector = <&apbdma 17>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                #address-cells = <1>;
                #size-cells = <0>;
                clocks = <&tegra_car 46>;
@@ -369,7 +369,7 @@
                reg = <0x0 0x7000da00 0x0 0x200>;
                interrupts = <0 93 0x04>;
                nvidia,dma-request-selector = <&apbdma 18>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                #address-cells = <1>;
                #size-cells = <0>;
                clocks = <&tegra_car 68>;
@@ -383,7 +383,7 @@
                reg = <0x0 0x7000dc00 0x0 0x200>;
                interrupts = <0 94 0x04>;
                nvidia,dma-request-selector = <&apbdma 27>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                #address-cells = <1>;
                #size-cells = <0>;
                clocks = <&tegra_car 104>;
@@ -397,7 +397,7 @@
                reg = <0x0 0x7000de00 0x0 0x200>;
                interrupts = <0 79 0x04>;
                nvidia,dma-request-selector = <&apbdma 28>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                #address-cells = <1>;
                #size-cells = <0>;
                clocks = <&tegra_car 105>;
@@ -627,8 +627,10 @@
                reg = <0x0 0x50000000 0x0 0x00034000>;
                interrupts = <0 65 0x04   /* mpcore syncpt */
                              0 67 0x04>; /* mpcore general */
-               iommus = <&smmu TEGRA_SWGROUP_CELLS4(EPP, HC, HDA, VDE)
-                         &common_as>;
+               iommus = <&smmu TEGRA_SWGROUP_EPP
+                         &smmu TEGRA_SWGROUP_HC
+                         &smmu TEGRA_SWGROUP_HDA
+                         &smmu TEGRA_SWGROUP_VDE>;
 
                #address-cells = <1>;
                #size-cells = <1>;
@@ -640,30 +642,31 @@
                        compatible = "nvidia,tegra124-vi";
                        reg = <0x54080000 0x00040000>;
                        interrupts = <0 69 0x04>;
-                       iommus = <&smmu TEGRA_SWGROUP_CELLS(VI) &common_as>;
+                       iommus = <&smmu TEGRA_SWGROUP_VI>;
                };
 
                isp@54600000 {
                        compatible = "nvidia,tegra124-isp";
                        reg = <0x54600000 0x00040000>;
                        interrupts = <0 71 0x04>;
-                       iommus = <&smmu TEGRA_SWGROUP_CELLS2(ISP, ISP2B)
-                                 &common_as>;
+                       iommus = <&smmu TEGRA_SWGROUP_ISP
+                                 &smmu TEGRA_SWGROUP_ISP2B>;
                };
 
                isp@54680000 {
                        compatible = "nvidia,tegra124-isp";
                        reg = <0x54680000 0x00040000>;
                        interrupts = <0 70 0x04>;
-                       iommus = <&smmu TEGRA_SWGROUP_CELLS2(ISP, ISP2B)
-                                 &common_as>;
+                       iommus = <&smmu TEGRA_SWGROUP_ISP
+                                 &smmu TEGRA_SWGROUP_ISP2B>;
                };
 
                dc@54200000 {
                        compatible = "nvidia,tegra124-dc";
                        reg = <0x54200000 0x00040000>;
                        interrupts = <0 73 0x04>;
-                       iommus = <&smmu TEGRA_SWGROUP_CELLS2(DC, DC12) &dc_as>;
+                       iommus = <&smmu TEGRA_SWGROUP_DC
+                                 &smmu TEGRA_SWGROUP_DC12>;
                        status = "disabled";
 
                        rgb {
@@ -675,7 +678,7 @@
                        compatible = "nvidia,tegra124-dc";
                        reg = <0x54240000 0x00040000>;
                        interrupts = <0 74 0x04>;
-                       iommus = <&smmu TEGRA_SWGROUP_CELLS(DCB) &dc_as>;
+                       iommus = <&smmu TEGRA_SWGROUP_DCB>;
                        status = "disabled";
 
                        rgb {
@@ -700,19 +703,19 @@
                vic {
                        compatible = "nvidia,tegra124-vic";
                        reg = <0x54340000 0x00040000>;
-                       iommus = <&smmu TEGRA_SWGROUP_CELLS(VIC) &common_as>;
+                       iommus = <&smmu TEGRA_SWGROUP_VIC>;
                };
 
                msenc {
                        compatible = "nvidia,tegra124-msenc";
                        reg = <0x544c0000 0x00040000>;
-                       iommus = <&smmu TEGRA_SWGROUP_CELLS(MSENC) &common_as>;
+                       iommus = <&smmu TEGRA_SWGROUP_MSENC>;
                };
 
                tsec {
                        compatible = "nvidia,tegra124-tsec";
                        reg = <0x54500000 0x00040000>;
-                       iommus = <&smmu TEGRA_SWGROUP_CELLS(TSEC) &common_as>;
+                       iommus = <&smmu TEGRA_SWGROUP_TSEC>;
                };
 
                sor {
@@ -743,7 +746,8 @@
                      <0x0 0x538F0000 0x0 0x00001000>;
                interrupts = <0 157 0x04
                              0 158 0x04>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS2(GPU, GPUB) &gpu_as>;
+               iommus = <&smmu TEGRA_SWGROUP_GPU
+                         &smmu TEGRA_SWGROUP_GPUB>;
        };
 
        xusb@70090000 {
@@ -839,7 +843,7 @@
                compatible = "nvidia,tegra124-sdhci";
                reg = <0x0 0x700b0600 0x0 0x200>;
                interrupts = < 0 31 0x04 >;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(SDMMC4A) &common_as>;
+               iommus = <&smmu TEGRA_SWGROUP_SDMMC4A>;
                status = "disabled";
                id = <3>;
        };
@@ -847,7 +851,7 @@
                compatible = "nvidia,tegra124-sdhci";
                reg = <0x0 0x700b0400 0x0 0x200>;
                interrupts = < 0 19 0x04 >;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(SDMMC3A) &common_as>;
+               iommus = <&smmu TEGRA_SWGROUP_SDMMC3A>;
                status = "disabled";
                id = <2>;
        };
@@ -855,7 +859,7 @@
                compatible = "nvidia,tegra124-sdhci";
                reg = <0x0 0x700b0200 0x0 0x200>;
                interrupts = < 0 15 0x04 >;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(SDMMC2A) &common_as>;
+               iommus = <&smmu TEGRA_SWGROUP_SDMMC2A>;
                status = "disabled";
                id = <1>;
        };
@@ -863,7 +867,7 @@
                compatible = "nvidia,tegra124-sdhci";
                reg = <0x0 0x700b0000 0x0 0x200>;
                interrupts = < 0 14 0x04 >;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(SDMMC1A) &common_as>;
+               iommus = <&smmu TEGRA_SWGROUP_SDMMC1A>;
                status = "disabled";
                id = <0>;
        };

diff --git a/arch/arm64/boot/dts/tegra210.dtsi b/arch/arm64/boot/dts/tegra210.dtsi
index 9f6704190f2e03581de666cd0767fb0d8102bb4b..347accd99523fffe7f59cb34d540740c053077bb 100644 (file)
--- a/arch/arm64/boot/dts/tegra210.dtsi
+++ b/arch/arm64/boot/dts/tegra210.dtsi
@@ -110,7 +110,7 @@
                       0x0 0x6000c000 0x0 0x1000>;
                #asids = <128>;
                dma-window = <0x0 0x80000000 0x0 0x7ff00000>;
-               #iommu-cells = <3>;
+               #iommu-cells = <1>;
                swgid-mask = <0x00000fff 0xfffccdcf>;
                #num-translation-enable = <5>;
                #num-asid-security = <8>;
@@ -343,7 +343,7 @@
                              0 97 0x04
                              0 21 0x04>;
                nvidia,hsic0 = /bits/8 <0x1 0x1 0x8 0xa 0 0 1 0x1c 0>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(XUSB_HOST) &common_as>;
+               iommus = <&smmu TEGRA_SWGROUP_XUSB_HOST>;
                status = "okay";
        };
 
@@ -352,7 +352,7 @@
                reg = <0x0 0x70006000 0x0 0x40>;
                reg-shift = <2>;
                interrupts = <0 36 0x04>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                 nvidia,dma-request-selector = <&apbdma 8>;
                 dmas = <&apbdma 8>, <&apbdma 8>;
                 dma-names = "rx", "tx";
@@ -364,7 +364,7 @@
                reg = <0x0 0x70006040 0x0 0x40>;
                reg-shift = <2>;
                interrupts = <0 37 0x04>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                 nvidia,dma-request-selector = <&apbdma 9>;
                 dmas = <&apbdma 9>, <&apbdma 9>;
                 dma-names = "rx", "tx";
@@ -377,7 +377,7 @@
                reg-shift = <2>;
                interrupts = <0 46 0x04>;
                nvidia,dma-request-selector = <&apbdma 10>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                dmas = <&apbdma 10>, <&apbdma 10>;
                dma-names = "rx", "tx";
                status = "disabled";
@@ -389,14 +389,14 @@
                reg-shift = <2>;
                interrupts = <0 90 0x04>;
                nvidia,dma-request-selector = <&apbdma 19>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                dmas = <&apbdma 19>, <&apbdma 19>;
                dma-names = "rx", "tx";
                status = "disabled";
        };
 
        sound {
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(APE) &ape_as>;
+               iommus = <&smmu TEGRA_SWGROUP_APE>;
        };
 
        sound_ref {
@@ -415,7 +415,7 @@
                reg = <0x0 0x7000d400 0x0 0x200>;
                interrupts = <0 59 0x04>;
                nvidia,dma-request-selector = <&apbdma 15>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                #address-cells = <1>;
                #size-cells = <0>;
                dmas = <&apbdma 15>, <&apbdma 15>;
@@ -428,7 +428,7 @@
                reg = <0x0 0x7000d600 0x0 0x200>;
                interrupts = <0 82 0x04>;
                nvidia,dma-request-selector = <&apbdma 16>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                #address-cells = <1>;
                #size-cells = <0>;
                dmas = <&apbdma 16>, <&apbdma 16>;
@@ -441,7 +441,7 @@
                reg = <0x0 0x7000d800 0x0 0x200>;
                interrupts = <0 83 0x04>;
                nvidia,dma-request-selector = <&apbdma 17>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                #address-cells = <1>;
                #size-cells = <0>;
                dmas = <&apbdma 17>, <&apbdma 17>;
@@ -454,7 +454,7 @@
                reg = <0x0 0x7000da00 0x0 0x200>;
                interrupts = <0 93 0x04>;
                nvidia,dma-request-selector = <&apbdma 18>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                #address-cells = <1>;
                #size-cells = <0>;
                dmas = <&apbdma 18>, <&apbdma 18>;
@@ -467,7 +467,7 @@
                reg = <0x0 0x70410000 0x0 0x1000>;
                interrupts = <0 10 0x04>;
                nvidia,dma-request-selector = <&apbdma 5>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                #address-cells = <1>;
                #size-cells = <0>;
                status = "disabled";
@@ -478,7 +478,7 @@
                reg = <0x0 0x50000000 0x0 0x00034000>;
                interrupts = <0 65 0x04   /* mpcore syncpt */
                              0 67 0x04>; /* mpcore general */
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(HC) &common_as>;
+               iommus = <&smmu TEGRA_SWGROUP_HC>;
 
                #address-cells = <2>;
                #size-cells = <2>;
@@ -489,34 +489,35 @@
                        compatible = "nvidia,tegra210-vi";
                        reg = <0x0 0x54080000 0x0 0x00040000>;
                        interrupts = <0 69 0x04>;
-                       iommus = <&smmu TEGRA_SWGROUP_CELLS(VI) &common_as>;
+                       iommus = <&smmu TEGRA_SWGROUP_VI>;
                };
 
                vii2c {
                        compatible = "nvidia,tegra210-vi-i2c";
                        reg = <0x0 0x546C0000 0x0 0x00034000>;
-                       iommus = <&smmu TEGRA_SWGROUP_CELLS(VII2C) &common_as>;
+                       iommus = <&smmu TEGRA_SWGROUP_VII2C>;
                };
 
                isp@54600000 {
                        compatible = "nvidia,tegra210-isp";
                        reg = <0x0 0x54600000 0x0 0x00040000>;
                        interrupts = <0 71 0x04>;
-                       iommus = <&smmu TEGRA_SWGROUP_CELLS(ISP) &common_as>;
+                       iommus = <&smmu TEGRA_SWGROUP_ISP>;
                };
 
                isp@54680000 {
                        compatible = "nvidia,tegra210-isp";
                        reg = <0x0 0x54680000 0x0 0x00040000>;
                        interrupts = <0 70 0x04>;
-                       iommus = <&smmu TEGRA_SWGROUP_CELLS(ISP2B) &common_as>;
+                       iommus = <&smmu TEGRA_SWGROUP_ISP2B>;
                };
 
                dc@54200000 {
                        compatible = "nvidia,tegra210-dc";
                        reg = <0x0 0x54200000 0x0 0x00040000>;
                        interrupts = <0 73 0x04>;
-                       iommus = <&smmu TEGRA_SWGROUP_CELLS2(DC, DC12) &dc_as>;
+                       iommus = <&smmu TEGRA_SWGROUP_DC
+                                 &smmu TEGRA_SWGROUP_DC12>;
                        status = "disabled";
 
                        rgb {
@@ -528,7 +529,7 @@
                        compatible = "nvidia,tegra210-dc";
                        reg = <0x0 0x54240000 0x0 0x00040000>;
                        interrupts = <0 74 0x04>;
-                       iommus = <&smmu TEGRA_SWGROUP_CELLS(DCB) &dc_as>;
+                       iommus = <&smmu TEGRA_SWGROUP_DCB>;
                        status = "disabled";
 
                        rgb {
@@ -546,37 +547,37 @@
                vic {
                        compatible = "nvidia,tegra210-vic";
                        reg = <0x0 0x54340000 0x0 0x00040000>;
-                       iommus = <&smmu TEGRA_SWGROUP_CELLS(VIC) &common_as>;
+                       iommus = <&smmu TEGRA_SWGROUP_VIC>;
                };
 
                nvenc {
                        compatible = "nvidia,tegra210-nvenc";
                        reg = <0x0 0x544c0000 0x0 0x00040000>;
-                       iommus = <&smmu TEGRA_SWGROUP_CELLS(MPE) &common_as>;
+                       iommus = <&smmu TEGRA_SWGROUP_MPE>;
                };
 
                tsec {
                        compatible = "nvidia,tegra210-tsec";
                        reg = <0x0 0x54500000 0x0 0x00040000>;
-                       iommus = <&smmu TEGRA_SWGROUP_CELLS(TSEC) &common_as>;
+                       iommus = <&smmu TEGRA_SWGROUP_TSEC>;
                };
 
                tsecb {
                        compatible = "nvidia,tegra210-tsec";
                        reg = <0x0 0x54100000 0x0 0x00040000>;
-                       iommus = <&smmu TEGRA_SWGROUP_CELLS(TSECB) &common_as>;
+                       iommus = <&smmu TEGRA_SWGROUP_TSECB>;
                };
 
                nvdec {
                        compatible = "nvidia,tegra210-nvdec";
                        reg = <0x0 0x54480000 0x0 0x00040000>;
-                       iommus = <&smmu TEGRA_SWGROUP_CELLS(NVDEC) &common_as>;
+                       iommus = <&smmu TEGRA_SWGROUP_NVDEC>;
                };
 
                nvjpg {
                        compatible = "nvidia,tegra210-nvjpg";
                        reg = <0x0 0x54380000 0x0 0x00040000>;
-                       iommus = <&smmu TEGRA_SWGROUP_CELLS(NVJPG) &common_as>;
+                       iommus = <&smmu TEGRA_SWGROUP_NVJPG>;
                };
 
                sor {
@@ -616,7 +617,8 @@
                    <0x0 0x538f0000 0x0 0x00001000>;
                    interrupts = <0 157 0x04
                            0 158 0x04>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS2(GPU, GPUB) &gpu_as>;
+               iommus = <&smmu TEGRA_SWGROUP_GPU
+                         &smmu TEGRA_SWGROUP_GPUB>;
        };
 
        mipical {
@@ -919,7 +921,7 @@
 
        tegra_adsp_audio: adsp_audio {
                compatible = "nvidia,tegra210-adsp-audio";
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(APE) &ape_as>;
+               iommus = <&smmu TEGRA_SWGROUP_APE>;
                status = "disabled";
        };
 
@@ -930,7 +932,7 @@
                   <0x0 0x702ee000 0x0 0x1000>, /* ABRIDGE */
                   <0x0 0x01000000 0x0 0x6f2c0000>, /* DRAM MAP1 */
                   <0x0 0x70300000 0x0 0x8fd00000>; /* DRAM MAP2 */
-            iommus = <&smmu TEGRA_SWGROUP_CELLS(APE) &ape_as>;
+            iommus = <&smmu TEGRA_SWGROUP_APE>;
             status = "okay";
        };
 
@@ -994,7 +996,7 @@
                reg = <0x0 0x70027000 0x0 0x00002000>,
                        <0x0 0x70021000 0x0 0x00001000>;
                interrupts = <0 23 0x04>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(SATA2) &common_as>;
+               iommus = <&smmu TEGRA_SWGROUP_SATA2>;
                status = "disabled";
        };
 
@@ -1004,7 +1006,7 @@
                compatible = "nvidia,tegra210-i2c";
                reg = <0x0 0x7000c000 0x0 0x100>;
                interrupts = <0 38 0x04>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                status = "okay";
                clock-frequency = <400000>;
        };
@@ -1015,7 +1017,7 @@
                compatible = "nvidia,tegra210-i2c";
                reg = <0x0 0x7000c400 0x0 0x100>;
                interrupts = <0 84 0x04>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                status = "okay";
                clock-frequency = <100000>;
        };
@@ -1026,7 +1028,7 @@
                compatible = "nvidia,tegra210-i2c";
                reg = <0x0 0x7000c500 0x0 0x100>;
                interrupts = <0 92 0x04>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                status = "okay";
                clock-frequency = <400000>;
        };
@@ -1037,7 +1039,7 @@
                compatible = "nvidia,tegra210-i2c";
                reg = <0x0 0x7000c700 0x0 0x100>;
                interrupts = <0 120 0x04>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                status = "okay";
                clock-frequency = <100000>;
        };
@@ -1051,7 +1053,7 @@
                scl-gpio = <&gpio 195 0>;
                sda-gpio = <&gpio 196 0>;
                nvidia,require-cldvfs-clock;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                status = "okay";
                clock-frequency = <400000>;
        };
@@ -1062,7 +1064,7 @@
                compatible = "nvidia,tegra210-i2c";
                reg = <0x0 0x7000d100 0x0 0x100>;
                interrupts = <0 63 0x04>;
-               iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS) &ppcs_as>;
+               iommus = <&smmu TEGRA_SWGROUP_PPCS>;
                status = "okay";
                clock-frequency = <400000>;
        };