iommu/tegra: smmu: modify pde/pte clean up

when all ptes in the level 2 page tables need to be cleared, remove
the pde entry pointing to this page table first.

This way, even if page tables are being cleared while a HW is doing
a page walk, it will never endup in a decoding error at level 2 page
table. The fate of page walk is decided at level 1 page table itself.

Bug 200063337

Change-Id: Ia8121bf915783a9b7e551a92299664e5ed9a0f3b
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/659675
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>

diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c
index b1bb4115ba3dc166e9d8c091f7308e489ed36a5c..3361a31788c59a87b7859d85e422aadab27c84bc 100644 (file)
--- a/drivers/iommu/tegra-smmu.c
+++ b/drivers/iommu/tegra-smmu.c
@@ -877,16 +877,17 @@ static size_t __smmu_iommu_unmap_pages(struct smmu_as *as, dma_addr_t iova,
                        unsigned int *rest = &as->pte_count[pdn];
                        size_t bytes = sizeof(*pte) * count;
 
-                       memset(pte, 0, bytes);
-                       FLUSH_CPU_DCACHE(pte, page, bytes);
-
                        for (i = 0; i < count; i++)
                                trace_smmu_set_pte(as->asid,
                                                   iova + i * PAGE_SIZE, 0,
                                                   PAGE_SIZE, 0);
                        *rest -= count;
-                       if (!*rest)
+                       if (*rest) {
+                               memset(pte, 0, bytes);
+                               FLUSH_CPU_DCACHE(pte, page, bytes);
+                       } else {
                                free_ptbl(as, iova, !flush_all);
+                       }
 
                        if (!flush_all)
                                flush_ptc_and_tlb_range(smmu, as, iova, pte,