Enable cache maint by set/ways on arm64.
Change-Id: I5b2fd41465403301c761d5a5b77811ca5b9824bb
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/357829
(cherry picked from commit
3d723cd30ac3fb289b4e08bbac34351b369c2055)
Reviewed-on: http://git-master/r/370122
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
select REPORT_PRESENT_CPUS if TEGRA_AUTO_HOTPLUG
select ARCH_SUPPORTS_MSI if TEGRA_PCI
select PCI_MSI if TEGRA_PCI
+ select NVMAP_CACHE_MAINT_BY_SET_WAYS if TEGRA_NVMAP
+ select NVMAP_CACHE_MAINT_BY_SET_WAYS_ON_ONE_CPU if TEGRA_NVMAP
select ARCH_TEGRA_HAS_CL_DVFS
select TEGRA_DYNAMIC_CBUS
select TEGRA_DUAL_CBUS
void inner_flush_cache_all(void)
{
-#if defined(CONFIG_ARM64)
+#if defined(CONFIG_ARM64) && defined(CONFIG_NVMAP_CACHE_MAINT_BY_SET_WAYS_ON_ONE_CPU)
+ __flush_dcache_all(NULL);
+#elif defined(CONFIG_ARM64)
on_each_cpu(__flush_dcache_all, NULL, 1);
#elif defined(CONFIG_NVMAP_CACHE_MAINT_BY_SET_WAYS_ON_ONE_CPU)
v7_flush_kern_cache_all();
#endif
}
-#ifndef CONFIG_ARM64
void inner_clean_cache_all(void)
{
+#if defined(CONFIG_ARM64)
+ inner_flush_cache_all();
+#else
#ifdef CONFIG_NVMAP_CACHE_MAINT_BY_SET_WAYS_ON_ONE_CPU
v7_clean_kern_cache_all(NULL);
#else
on_each_cpu(v7_clean_kern_cache_all, NULL, 1);
#endif
-}
#endif
+}
void nvmap_flush_cache(struct page **pages, int numpages)
{
extern struct nvmap_share *nvmap_share;
/* holds max number of handles allocted per process at any time */
extern u32 nvmap_max_handle_count;
+extern size_t cache_maint_inner_threshold;
extern struct platform_device *nvmap_pdev;
#define outer_flush_range(s, e)
#define outer_inv_range(s, e)
#define outer_clean_range(s, e)
+#define outer_flush_all()
extern void __flush_dcache_page(struct page *);
#else
#define PG_PROT_KERNEL pgprot_kernel