ARM: tegra: pcie: Enable ASPM l1 state support

Currently, only L0s state of ASPM is supported by default.
This change enables the l1 state support for Root Ports.

Bug 815499

Change-Id: Iec5e5f2edbf4ccfa35cb74432e18b29f18ec7771
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: http://git-master/r/110062
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jay Agarwal <jagarwal@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Rebase-Id: R05e620c037767343de64208fe6841b93e7842b0c

diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 54e3e140d3d402a1744f4dc0de51c2ed6a9763bc..6ecc1be526d39504c155541b6def29a99bcfee58 100644 (file)
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -215,6 +215,9 @@
 #define PCIE2_RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE               1 << 23
 #define PCIE2_RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE                1 << 31
 
+#define NV_PCIE2_RP_VEND_XP1                                   0x00000F04
+#define NV_PCIE2_RP_VEND_XP1_LINK_PVT_CTL_L1_ASPM_SUPPORT_ENABLE       1 << 21
+
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 /*
  * Tegra2 defines 1GB in the AXI address map for PCIe.
@@ -1092,7 +1095,7 @@ retry:
        return false;
 }
 
-static void tegra_enable_clock_clamp(int index)
+static void tegra_pcie_enable_clock_clamp(int index)
 {
        unsigned int data;
 
@@ -1104,6 +1107,16 @@ static void tegra_enable_clock_clamp(int index)
        rp_writel(data, NV_PCIE2_RP_PRIV_MISC, index);
 }
 
+static void tegra_pcie_enable_aspm_l1_support(int index)
+{
+       unsigned int data;
+
+       /* Enable ASPM - L1 state support by default */
+       data = rp_readl(NV_PCIE2_RP_VEND_XP1, index);
+       data |= (NV_PCIE2_RP_VEND_XP1_LINK_PVT_CTL_L1_ASPM_SUPPORT_ENABLE);
+       rp_writel(data, NV_PCIE2_RP_VEND_XP1, index);
+}
+
 static void tegra_pcie_add_port(int index, u32 offset, u32 reset_reg)
 {
        struct tegra_pcie_port *pp;
@@ -1119,7 +1132,8 @@ static void tegra_pcie_add_port(int index, u32 offset, u32 reset_reg)
                printk(KERN_INFO "PCIE: port %d: link down, ignoring\n", index);
                return;
        }
-       tegra_enable_clock_clamp(index);
+       tegra_pcie_enable_clock_clamp(index);
+       tegra_pcie_enable_aspm_l1_support(index);
        tegra_pcie.num_ports++;
        pp->index = index;
        memset(pp->res, 0, sizeof(pp->res));