ARM: tegra: disable active discharge for cpu/core/gpu rail for T132 platforms

Disable active discharge on idle for cpu, core and gpu rail for Palmas based
T132 platforms.

The active discharge will be enable on suspend and shutdown. On resume,
it get disabled again.

bug 1454238

Change-Id: I66626de978418eff046fd5d39eff054c4cbd4dd2
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/406341
GVS: Gerrit_Virtual_Submit

diff --git a/arch/arm64/boot/dts/tegra132-bowmore-e1971-1100-a00-00.dts b/arch/arm64/boot/dts/tegra132-bowmore-e1971-1100-a00-00.dts
index 472c49aa0ebd0c18b9b6436292b6b935b8990a26..fb249734857a2444e5d7353af2eeb939b3e58be0 100644 (file)
--- a/arch/arm64/boot/dts/tegra132-bowmore-e1971-1100-a00-00.dts
+++ b/arch/arm64/boot/dts/tegra132-bowmore-e1971-1100-a00-00.dts
@@ -32,6 +32,19 @@
                        thermal {
                                status = "okay";
                        };
+                       pmic {
+                               regulators {
+                                       smps123 {
+                                               ti,disable-active-discharge-idle;
+                                       };
+                                       smps45 {
+                                               ti,disable-active-discharge-idle;
+                                       };
+                                       smps7 {
+                                               ti,disable-active-discharge-idle;
+                                       };
+                               };
+                       };
                };
        };
 

diff --git a/arch/arm64/boot/dts/tegra132-tn8-p1761-1270-a03.dts b/arch/arm64/boot/dts/tegra132-tn8-p1761-1270-a03.dts
index 985b2c0cd8e8e56cc46a84376da58bc419500f93..9484ae0cc5ac5eb055ea044032526c25f912375c 100644 (file)
--- a/arch/arm64/boot/dts/tegra132-tn8-p1761-1270-a03.dts
+++ b/arch/arm64/boot/dts/tegra132-tn8-p1761-1270-a03.dts
@@ -32,6 +32,19 @@
                        thermal {
                                status = "okay";
                        };
+                       pmic {
+                               regulators {
+                                       smps123 {
+                                               ti,disable-active-discharge-idle;
+                                       };
+                                       smps45 {
+                                               ti,disable-active-discharge-idle;
+                                       };
+                                       smps7 {
+                                               ti,disable-active-discharge-idle;
+                                       };
+                               };
+                       };
                };
        };
 };