Revert "mmc: host: tegra: fixup NVQUIRKS ordering."

This reverts commit cae15f158420e1b58f6477db93799a81e88148c1.

This is temporarily reverted to bring in the latest changes from main-3.8 as part of http://git-master/r/#/c/275425/1

Change-Id: Ibd3f87ded263485fb50d1e2390205e31dee2c2ce
Reviewed-on: http://git-master/r/276124
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 40ab9c2d68b01dacb5bd2fa6c917ae416f2c6a19..5530d38f8517e75e71e9b48edd140e79b876e3ec 100644 (file)
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -169,14 +169,14 @@ static unsigned int uhs_max_freq_MHz[] = {
 /* update PAD_E_INPUT_OR_E_PWRD bit */
 #define NVQUIRK_SET_PAD_E_INPUT_OR_E_PWRD      BIT(18)
 /* Shadow write xfer mode reg and write it alongwith CMD register */
-#define NVQUIRK_SHADOW_XFER_MODE_REG           BIT(19)
+#define NVQUIRK_SHADOW_XFER_MODE_REG           BIT(18)
 /* In SDR50 mode, run the sdmmc controller at freq greater than
  * 104MHz to ensure the core voltage is at 1.2V. If the core voltage
  * is below 1.2V, CRC errors would occur during data transfers
  */
-#define NVQUIRK_BROKEN_SDR50_CONTROLLER_CLOCK  BIT(20)
+#define NVQUIRK_BROKEN_SDR50_CONTROLLER_CLOCK  BIT(19)
 /* Set Pipe stages value o zero */
-#define NVQUIRK_SET_PIPE_STAGES_MASK_0         BIT(21)
+#define NVQUIRK_SET_PIPE_STAGES_MASK_0         BIT(20)
 
 struct sdhci_tegra_soc_data {
        const struct sdhci_pltfm_data *pdata;