ARM: tegra: dvfs: Change CPU VSEL access attribute

Changed CPU voltage selector register access to volatile/cached when
switching rail to/from DFLL mode, respectively. Added debug prints to
facilitate debugging.

Bug 1454969

Change-Id: Ic5176d99f8a179bca9baef4296ef45df66db7f0e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/365780
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

diff --git a/arch/arm/mach-tegra/dvfs.c b/arch/arm/mach-tegra/dvfs.c
index ae544dccb03a80fec580bd2e2c4f747533092ad2..869b6894244a09c8d0eaf947b00881e7f7e2ae58 100644 (file)
--- a/arch/arm/mach-tegra/dvfs.c
+++ b/arch/arm/mach-tegra/dvfs.c
@@ -260,6 +260,9 @@ static int dvfs_rail_set_voltage_reg(struct dvfs_rail *rail, int millivolts)
                rail->reg_max_millivolts * 1000);
        rail->updating = false;
 
+       pr_debug("%s: request_mV [%d, %d] from %s regulator (%d)\n", __func__,
+                millivolts, rail->reg_max_millivolts, rail->reg_id, ret);
+
        return ret;
 }
 
@@ -1539,6 +1542,14 @@ int tegra_dvfs_dfll_mode_set(struct dvfs *d, unsigned long rate)
        if (!d->dvfs_rail->dfll_mode) {
                d->dvfs_rail->dfll_mode = true;
                __tegra_dvfs_set_rate(d, rate);
+
+               /*
+                * Report error, but continue: DFLL is functional, anyway, and
+                * no error with proper regulator driver update
+                */
+               if (regulator_set_vsel_volatile(d->dvfs_rail->reg, true))
+                       WARN_ONCE(1, "%s: failed to set vsel volatile\n",
+                                 __func__);
        }
        mutex_unlock(&dvfs_lock);
        return 0;
@@ -1551,6 +1562,8 @@ int tegra_dvfs_dfll_mode_clear(struct dvfs *d, unsigned long rate)
        mutex_lock(&dvfs_lock);
        if (d->dvfs_rail->dfll_mode) {
                d->dvfs_rail->dfll_mode = false;
+               regulator_set_vsel_volatile(d->dvfs_rail->reg, false);
+
                /* avoid false detection of matching target (voltage in dfll
                   mode is fluctuating, and recorded level is just estimate) */
                d->dvfs_rail->millivolts--;