ARM: tegra: clock: Don't set PLLE VREG controls

Kept PLLE VREG controls default state (cleared) to match PROD settings.

Bug 1490429

Change-Id: I3f253c968e096685196d24a04d6801eb1b1050ad
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/393597
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

diff --git a/arch/arm/mach-tegra/tegra12_clocks.c b/arch/arm/mach-tegra/tegra12_clocks.c
index cbf67a26f4ef490796662ec253691aa92ff793b0..6676cdb3d8137d3c9a9f000a955a3d03b78aca22 100644 (file)
--- a/arch/arm/mach-tegra/tegra12_clocks.c
+++ b/arch/arm/mach-tegra/tegra12_clocks.c
@@ -4189,7 +4189,6 @@ static int tegra12_plle_clk_enable(struct clk *c)
        val |= PLLE_MISC_IDDQ_SW_CTRL;
        val &= ~PLLE_MISC_IDDQ_SW_VALUE;
        val |= PLLE_MISC_PLLE_PTS;
-       val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
        clk_writel(val, c->reg + PLL_MISC(c));
        udelay(5);