ARM: tegra12: dvfs: Set CPU rate limit to 2.2GHz

Set CPU rate limit to 2.2GHz for Tegra12 sku 0x27.

Bug 1475295

Change-Id: Ia96011bf398dfb35721b201bd799ea66e9cdf78e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/381750
(cherry-picked from commit f703fdc9373905a82437f673ab557c32ac63c59c)
Reviewed-on: http://git-master/r/384840
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

diff --git a/arch/arm/mach-tegra/tegra12_dvfs.c b/arch/arm/mach-tegra/tegra12_dvfs.c
index c6ae432e7a3a6d193f7d312dc8a5a5febce601e8..e050570a16b13ce5a9659107e6c9412a9e285797 100644 (file)
--- a/arch/arm/mach-tegra/tegra12_dvfs.c
+++ b/arch/arm/mach-tegra/tegra12_dvfs.c
@@ -147,8 +147,8 @@ void __init tegra12x_vdd_cpu_align(int step_uv, int offset_uv)
 
 /* CPU DVFS tables */
 static unsigned long cpu_max_freq[] = {
-/* speedo_id   0        1        2        3            4  */
-               2014500, 2320500, 2116500, 2524500, 1500000,
+/* speedo_id   0        1        2        3        4        5       */
+               2014500, 2320500, 2116500, 2524500, 1500000, 2218500,
 };
 
 static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = {

diff --git a/arch/arm/mach-tegra/tegra12_edp.c b/arch/arm/mach-tegra/tegra12_edp.c
index d0c3455545fa07635820012d8e7d22f6b4be3794..84f026618ce19af395b3ffb978dc8b4540666029 100644 (file)
--- a/arch/arm/mach-tegra/tegra12_edp.c
+++ b/arch/arm/mach-tegra/tegra12_edp.c
@@ -204,6 +204,7 @@ struct tegra_sysedp_corecap *tegra_get_sysedp_corecap(unsigned int *sz)
        gpu_speedo_id = tegra_gpu_speedo_id();
 
        switch (cpu_speedo_id) {
+       case 0x5:
        case 0x2:
                if (gpu_speedo_id == 1) {
                        /* 575 variants */
@@ -316,6 +317,10 @@ static struct tegra_edp_cpu_leakage_params t12x_leakage_params[] = {
                .cpu_speedo_id      = 3, /* Prod SKU */
                EDP_PARAMS_COMMON_PART,
        },
+       {
+               .cpu_speedo_id      = 5, /* Prod SKU */
+               EDP_PARAMS_COMMON_PART,
+       },
 };
 
 #ifdef CONFIG_TEGRA_GPU_EDP

diff --git a/arch/arm/mach-tegra/tegra12_speedo.c b/arch/arm/mach-tegra/tegra12_speedo.c
index 1042adbfd662fc17097bc037c4365477838b7255..a9dd9c474c06e16134afd87ec01b2a4aa4144479 100644 (file)
--- a/arch/arm/mach-tegra/tegra12_speedo.c
+++ b/arch/arm/mach-tegra/tegra12_speedo.c
@@ -106,7 +106,7 @@ static void rev_sku_to_speedo_ids(int rev, int sku)
        case 0x1F:
        case 0x87:
        case 0x27:
-               cpu_speedo_id = 2;
+               cpu_speedo_id = sku == 0x27 ? 5 : 2;
                soc_speedo_id = 0;
                gpu_speedo_id = 1;
                threshold_index = 0;