]> rtime.felk.cvut.cz Git - sojka/nv-tegra/linux-3.10.git/commitdiff
ARM: tegra: sdmmc pwrdet API
authorBitan Biswas <bbiswas@nvidia.com>
Wed, 20 Aug 2014 10:13:34 +0000 (15:43 +0530)
committerTom Cherry <tcherry@nvidia.com>
Wed, 27 Aug 2014 19:00:07 +0000 (12:00 -0700)
API to write SDMMC1 and SDMMC3 power detect
bit defined. Tegra21x needs this to enable
voltage switch for SD 3.0 cards.

Change-Id: Iecc7a8a41065af9046460623a31c31974ab822a7
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/482449
GVS: Gerrit_Virtual_Submit
Tested-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
arch/arm/mach-tegra/powerdetect.c
drivers/platform/tegra/pmc.c
include/linux/tegra-pmc.h

index 114c661c494fcaf1b470cc8fb976f6c6635207eb..ff83e9ce2278843b33018f47a7718cdd45b135c7 100644 (file)
@@ -29,6 +29,7 @@
 #include <linux/module.h>
 #include <linux/tegra-soc.h>
 #include <linux/tegra-fuse.h>
+#include <linux/tegra-pmc.h>
 
 #include "board.h"
 #include "iomap.h"
@@ -92,6 +93,34 @@ static struct pwr_detect_cell pwr_detect_cells[] = {
        POWER_CELL("pwrdet-hv",         (0x1 << 15), (0x1 << 15), 0xFFFFFFFF),
 };
 
+void pwr_detect_bit_write(u32 pwrdet_bit, bool enable)
+{
+       unsigned int pwrdet_mask;
+       pwrdet_mask = pmc_readl(PMC_PWR_DET_ENABLE);
+       switch (pwrdet_bit) {
+       case SDMMC1_PWR_DET:
+       case SDMMC3_PWR_DET:
+               if (!(pwrdet_mask & (BIT(pwrdet_bit)))) {
+                       pwrdet_mask |= BIT(pwrdet_bit);
+                       pmc_writel(pwrdet_mask, PMC_PWR_DET_ENABLE);
+               }
+               pwrdet_mask = pmc_readl(PMC_PWR_DET_VAL);
+               if ((pwrdet_mask & (BIT(pwrdet_bit))) && !enable) {
+                       pwrdet_mask &= ~(BIT(pwrdet_bit));
+                       pmc_writel(pwrdet_mask, PMC_PWR_DET_VAL);
+                       udelay(100);
+               } else if (enable && !(pwrdet_mask & (BIT(pwrdet_bit)))) {
+                       pwrdet_mask |= BIT(pwrdet_bit);
+                       pmc_writel(pwrdet_mask, PMC_PWR_DET_VAL);
+                       udelay(100);
+               }
+               break;
+       default:
+               return;
+       }
+}
+EXPORT_SYMBOL(pwr_detect_bit_write);
+
 static void pwr_detect_reset(u32 pwrdet_mask)
 {
        pmc_writel(pwrdet_mask, PMC_PWR_DET_ENABLE);
index 697c22ccbc0c0835681343317af500c3d4766cf5..77d381e5c85c19c1f2ee3d926f23c5187175e748 100644 (file)
@@ -94,6 +94,11 @@ static bool tegra_pmc_invert_interrupt;
 static struct clk *tegra_pclk;
 #endif
 
+#ifndef CONFIG_TEGRA_DYNAMIC_PWRDET
+void pwr_detect_bit_write(u32 pwrdet_bit, bool enable) { }
+EXPORT_SYMBOL(pwr_detect_bit_write);
+#endif
+
 #ifdef CONFIG_OF
 static struct pmc_pm_data pmc_pm_data;
 #endif
index cc803c89dc94a612ae1fd93dfae645224079facc..8d040c4802c208f0a5a55e5027e8414277f4da7b 100644 (file)
@@ -108,4 +108,11 @@ extern void tegra_pmc_config_thermal_trip(struct tegra_thermtrip_pmic_data *data
 
 extern void tegra_pmc_enable_thermal_trip(void);
 
+enum pwrdet_bit {
+       SDMMC1_PWR_DET = 12,
+       SDMMC3_PWR_DET = 13
+};
+
+extern void pwr_detect_bit_write(u32 pwrdet_bit, bool enable);
+
 #endif /* __LINUX_TEGRA_PMC_H__ */