dvfs: tegra21: Integrate p4v47 Vmin binning scheme

Bug 1558421

Change-Id: If36eb7b005a20dc286591bba5968da72f62a6f76
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/757658
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

diff --git a/drivers/platform/tegra/tegra21_dvfs.c b/drivers/platform/tegra/tegra21_dvfs.c
index 38728070bf01a79fdb8e4db5d1cdef97fe6f09bf..f743d3430a64f1398f3ce744dd8d38513c977f46 100644 (file)
--- a/drivers/platform/tegra/tegra21_dvfs.c
+++ b/drivers/platform/tegra/tegra21_dvfs.c
@@ -106,7 +106,7 @@ static struct dvfs_rail tegra21_dvfs_rail_vdd_core = {
        .alignment = {
                .step_uv = 12500, /* 12.5mV */
        },
-       .version = "p4v40_p4Av05",
+       .version = "p4v47_p4Av05",
 };
 
 static struct dvfs_rail tegra21_dvfs_rail_vdd_gpu = {
@@ -123,7 +123,7 @@ static struct dvfs_rail tegra21_dvfs_rail_vdd_gpu = {
        .stats = {
                .bin_uV = 6250, /* 6.25mV */
        },
-       .version = "p4v40_p4Av05",
+       .version = "p4v45_p4Av05",
 };
 
 static struct dvfs_rail *tegra21_dvfs_rails[] = {
@@ -235,7 +235,7 @@ static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = {
                        .tune_high_min_millivolts = 903,
                        .tune1          = 0x020091D9,
                        .droop_rate_min = 1000000,
-                       .min_millivolts = 830,
+                       .min_millivolts = 870,
                },
                .pll_tune_data = {
                        .min_millivolts = 950,
@@ -247,6 +247,24 @@ static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = {
        {
                .speedo_id = 3,
                .process_id = 1,
+               .dfll_tune_data  = {
+                       .tune0          = 0xFFEAD0FF,
+                       .tune0_high_mv  = 0xFFEAD0FF,
+                       .tune_high_min_millivolts = 903,
+                       .tune1          = 0x020091D9,
+                       .droop_rate_min = 1000000,
+                       .min_millivolts = 830,
+               },
+               .pll_tune_data = {
+                       .min_millivolts = 950,
+               },
+               .max_mv = 1227,
+               .max_freq = 2218500,
+               CPU_CVB_TABLE,
+       },
+       {
+               .speedo_id = 3,
+               .process_id = 2,
                .dfll_tune_data  = {
                        .tune0          = 0xFFEAD0FF,
                        .tune0_high_mv  = 0xFFEAD0FF,
@@ -309,7 +327,7 @@ static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = {
                        .tune_high_min_millivolts = 903,
                        .tune1          = 0x020091D9,
                        .droop_rate_min = 1000000,
-                       .min_millivolts = 800,
+                       .min_millivolts = 850,
                },
                .pll_tune_data = {
                        .min_millivolts = 950,
@@ -321,6 +339,24 @@ static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = {
        {
                .speedo_id = 1,
                .process_id = 1,
+               .dfll_tune_data  = {
+                       .tune0          = 0xFFEAD0FF,
+                       .tune0_high_mv  = 0xFFEAD0FF,
+                       .tune_high_min_millivolts = 903,
+                       .tune1          = 0x020091D9,
+                       .droop_rate_min = 1000000,
+                       .min_millivolts = 800,
+               },
+               .pll_tune_data = {
+                       .min_millivolts = 950,
+               },
+               .max_mv = 1170,
+               .max_freq = 1912500,
+               CPU_CVB_TABLE,
+       },
+       {
+               .speedo_id = 1,
+               .process_id = 2,
                .dfll_tune_data  = {
                        .tune0          = 0xFFEAD0FF,
                        .tune0_high_mv  = 0xFFEAD0FF,
@@ -438,7 +474,17 @@ static struct cpu_cvb_dvfs cpu_lp_cvb_dvfs_table[] = {
        },
        {
                .speedo_id = 1,
-               .process_id = -1,
+               .process_id = 1,
+               .pll_tune_data = {
+                       .min_millivolts = 800,
+               },
+               .max_mv = 1170,
+               .max_freq = 1132800,
+               CPU_LP_CVB_TABLE,
+       },
+       {
+               .speedo_id = 1,
+               .process_id = 2,
                .pll_tune_data = {
                        .min_millivolts = 800,
                },
@@ -549,11 +595,26 @@ static struct gpu_cvb_dvfs gpu_cvb_dvfs_table[] = {
                FIXED_FREQ_CVB_TABLE,
 #endif
        },
+
        {
                .speedo_id = 4,
-               .process_id = -1,
+               .process_id = 0,
                .pll_tune_data = {
-                       .min_millivolts = 800,
+                       .min_millivolts = 840,
+               },
+               .max_mv = 1150,
+               .max_freq = 921600,
+#ifdef CONFIG_TEGRA_USE_NA_GPCPLL
+               NA_FREQ_CVB_TABLE,
+#else
+               FIXED_FREQ_CVB_TABLE,
+#endif
+       },
+       {
+               .speedo_id = 4,
+               .process_id = 1,
+               .pll_tune_data = {
+                       .min_millivolts = 810,
                },
                .max_mv = 1150,
                .max_freq = 921600,
@@ -563,6 +624,7 @@ static struct gpu_cvb_dvfs gpu_cvb_dvfs_table[] = {
                FIXED_FREQ_CVB_TABLE,
 #endif
        },
+
        {
                .speedo_id = 3,
                .process_id = -1,
@@ -577,11 +639,26 @@ static struct gpu_cvb_dvfs gpu_cvb_dvfs_table[] = {
                FIXED_FREQ_CVB_TABLE,
 #endif
        },
+
        {
                .speedo_id = 2,
-               .process_id = -1,
+               .process_id = 0,
                .pll_tune_data = {
-                       .min_millivolts = 800,
+                       .min_millivolts = 840,
+               },
+               .max_mv = 1150,
+               .max_freq = 998400,
+#ifdef CONFIG_TEGRA_USE_NA_GPCPLL
+               NA_FREQ_CVB_TABLE,
+#else
+               FIXED_FREQ_CVB_TABLE,
+#endif
+       },
+       {
+               .speedo_id = 2,
+               .process_id = 1,
+               .pll_tune_data = {
+                       .min_millivolts = 810,
                },
                .max_mv = 1150,
                .max_freq = 998400,
@@ -591,6 +668,7 @@ static struct gpu_cvb_dvfs gpu_cvb_dvfs_table[] = {
                FIXED_FREQ_CVB_TABLE,
 #endif
        },
+
        {
                .speedo_id = 1,
                .process_id = -1,
@@ -605,6 +683,7 @@ static struct gpu_cvb_dvfs gpu_cvb_dvfs_table[] = {
                FIXED_FREQ_CVB_TABLE,
 #endif
        },
+
        {
                .speedo_id = 0,
                .process_id = -1,

diff --git a/drivers/platform/tegra/tegra21_speedo.c b/drivers/platform/tegra/tegra21_speedo.c
index ad30d1b798c4133eae085ae655cf6581ddbeee23..04d05fabdf08c67d5502e8212919ff209aaa4da2 100644 (file)
--- a/drivers/platform/tegra/tegra21_speedo.c
+++ b/drivers/platform/tegra/tegra21_speedo.c
@@ -37,7 +37,7 @@
 #define TEGRA21_GPU_SPEEDO_OFFS 75
 
 
-#define CPU_PROCESS_CORNERS_NUM                2
+#define CPU_PROCESS_CORNERS_NUM                3
 #define GPU_PROCESS_CORNERS_NUM                2
 #define CORE_PROCESS_CORNERS_NUM       3
 
@@ -83,21 +83,24 @@ static int speedo_rev;
 static int enable_app_profiles;
 
 static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = {
-/* proc_id  0,       1 */
-       {2119,  UINT_MAX}, /* [0]: threshold_index 0 */
-       {2119,  UINT_MAX}, /* [1]: threshold_index 1 */
+/* proc_id  0,        1          2 */
+       {2119,  UINT_MAX,  UINT_MAX}, /* [0]: threshold_index 0 */
+       {2031,  2119,      UINT_MAX}, /* [1]: threshold_index 1 */
+       {2119,  UINT_MAX,  UINT_MAX}, /* [2]: threshold_index 2 */
 };
 
 static const u32 gpu_process_speedos[][GPU_PROCESS_CORNERS_NUM] = {
 /* proc_id      0,        1 */
        {UINT_MAX, UINT_MAX}, /* [0]: threshold_index 0 */
-       {UINT_MAX, UINT_MAX}, /* [1]: threshold_index 1 */
+       {2009,     UINT_MAX}, /* [1]: threshold_index 1 */
+       {UINT_MAX, UINT_MAX}, /* [2]: threshold_index 2 */
 };
 
 static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
-/* proc_id  0,    1,         2 */
-       {1950,  2100,  UINT_MAX}, /* [0]: threshold_index 0 */
-       {UINT_MAX,  UINT_MAX,  UINT_MAX}, /* [1]: threshold_index 1 */
+/* proc_id  0,        1,             2 */
+       {1950,      2100,      UINT_MAX}, /* [0]: threshold_index 0 */
+       {1950,      2100,      UINT_MAX}, /* [1]: threshold_index 1 */
+       {UINT_MAX,  UINT_MAX,  UINT_MAX}, /* [2]: threshold_index 2 */
 };
 
 static void rev_sku_to_speedo_ids(int rev, int sku, int speedo_rev)
@@ -113,27 +116,25 @@ static void rev_sku_to_speedo_ids(int rev, int sku, int speedo_rev)
                                               "nvidia,t210-vcm31-sku");
 #endif
        switch (sku) {
-       case 0x01: /* Engg sku */
-       case 0x13:
-               if (a02) {
-                       cpu_speedo_id = shield_sku ? 3 : 1;
-                       soc_speedo_id = 0;
-                       gpu_speedo_id = 2;
-                       threshold_index = 0;
-                       core_min_mv = 800;
-                       break;
-               }
-               /* fall thru for a01 */
        case 0x00: /* Engg sku */
+       case 0x01: /* Engg sku */
        case 0x07:
        case 0x17:
-       case 0x27:
+       case 0x13:
                if (!vcm31_sku || (sku != 0x17)) {
-                       cpu_speedo_id = shield_sku ? 2 : 0;
-                       soc_speedo_id = 0;
-                       gpu_speedo_id = 1;
-                       threshold_index = 0;
-                       core_min_mv = 825;
+                       if (a02) {
+                               cpu_speedo_id = shield_sku ? 3 : 1;
+                               soc_speedo_id = 0;
+                               gpu_speedo_id = 2;
+                               threshold_index = 1;
+                               core_min_mv = 800;
+                       } else {
+                               cpu_speedo_id = shield_sku ? 2 : 0;
+                               soc_speedo_id = 0;
+                               gpu_speedo_id = 1;
+                               threshold_index = 0;
+                               core_min_mv = 825;
+                       }
                        break;
                }
                /* fall thru for vcm31_sku 0x17 */
@@ -141,25 +142,24 @@ static void rev_sku_to_speedo_ids(int rev, int sku, int speedo_rev)
                cpu_speedo_id = 4;
                soc_speedo_id = 1;
                gpu_speedo_id = 5;
-               threshold_index = 1;
+               threshold_index = 2;
                core_min_mv = 1100;
                break;
        case 0x83:
+       case 0x87:
                if (a02) {
-                       cpu_speedo_id = 1;
+                       cpu_speedo_id = (shield_sku && (sku == 0x87)) ? 3 : 1;
                        soc_speedo_id = 0;
                        gpu_speedo_id = 4;
-                       threshold_index = 0;
+                       threshold_index = 1;
                        core_min_mv = 800;
-                       break;
+               } else {
+                       cpu_speedo_id = 0;
+                       soc_speedo_id = 0;
+                       gpu_speedo_id = 3;
+                       threshold_index = 0;
+                       core_min_mv = 825;
                }
-               /* fall thru for a01 */
-       case 0x87:
-               cpu_speedo_id = (shield_sku && a02) ? 2 : 0;
-               soc_speedo_id = 0;
-               gpu_speedo_id = 3;
-               threshold_index = 0;
-               core_min_mv = 825;
                break;
        default:
                pr_warn("Tegra21: Unknown SKU %d\n", sku);
@@ -406,6 +406,10 @@ int tegra_core_speedo_mv(void)
 
 int tegra_core_speedo_min_mv(void)
 {
+       /* Overwrite Vmin for lower bin with fixed value */
+       if ((soc_speedo_id == 0) && (core_process_id == 0))
+               return 825;
+
        return core_min_mv;
 }